392 lines
9.5 KiB
C
392 lines
9.5 KiB
C
/*
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* linux/drivers/clocksource/arm_arch_timer.c
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*
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* Copyright (C) 2011 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <linux/cpu.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/of_irq.h>
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#include <linux/io.h>
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#include <asm/arch_timer.h>
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#include <asm/virt.h>
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#include <clocksource/arm_arch_timer.h>
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static u32 arch_timer_rate;
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enum ppi_nr {
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PHYS_SECURE_PPI,
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PHYS_NONSECURE_PPI,
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VIRT_PPI,
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HYP_PPI,
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MAX_TIMER_PPI
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};
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static int arch_timer_ppi[MAX_TIMER_PPI];
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static struct clock_event_device __percpu *arch_timer_evt;
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static bool arch_timer_use_virtual = true;
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/*
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* Architected system timer support.
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*/
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static inline irqreturn_t timer_handler(const int access,
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struct clock_event_device *evt)
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{
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unsigned long ctrl;
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ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
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if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
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ctrl |= ARCH_TIMER_CTRL_IT_MASK;
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arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
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}
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static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
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}
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static inline void timer_set_mode(const int access, int mode)
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{
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unsigned long ctrl;
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switch (mode) {
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
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ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
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arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
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break;
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default:
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break;
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}
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}
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static void arch_timer_set_mode_virt(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode);
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}
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static void arch_timer_set_mode_phys(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode);
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}
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static inline void set_next_event(const int access, unsigned long evt)
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{
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unsigned long ctrl;
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ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
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ctrl |= ARCH_TIMER_CTRL_ENABLE;
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ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
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arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
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arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
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}
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static int arch_timer_set_next_event_virt(unsigned long evt,
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struct clock_event_device *unused)
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{
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set_next_event(ARCH_TIMER_VIRT_ACCESS, evt);
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return 0;
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}
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static int arch_timer_set_next_event_phys(unsigned long evt,
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struct clock_event_device *unused)
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{
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set_next_event(ARCH_TIMER_PHYS_ACCESS, evt);
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return 0;
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}
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static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
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{
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clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
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clk->name = "arch_sys_timer";
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clk->rating = 450;
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if (arch_timer_use_virtual) {
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clk->irq = arch_timer_ppi[VIRT_PPI];
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clk->set_mode = arch_timer_set_mode_virt;
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clk->set_next_event = arch_timer_set_next_event_virt;
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} else {
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clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
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clk->set_mode = arch_timer_set_mode_phys;
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clk->set_next_event = arch_timer_set_next_event_phys;
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}
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clk->cpumask = cpumask_of(smp_processor_id());
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clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, NULL);
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clockevents_config_and_register(clk, arch_timer_rate,
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0xf, 0x7fffffff);
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if (arch_timer_use_virtual)
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enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
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else {
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enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
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if (arch_timer_ppi[PHYS_NONSECURE_PPI])
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enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
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}
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arch_counter_set_user_access();
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return 0;
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}
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static int arch_timer_available(void)
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{
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u32 freq;
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if (arch_timer_rate == 0) {
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freq = arch_timer_get_cntfrq();
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/* Check the timer frequency. */
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if (freq == 0) {
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pr_warn("Architected timer frequency not available\n");
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return -EINVAL;
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}
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arch_timer_rate = freq;
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}
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pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
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(unsigned long)arch_timer_rate / 1000000,
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(unsigned long)(arch_timer_rate / 10000) % 100,
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arch_timer_use_virtual ? "virt" : "phys");
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return 0;
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}
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u32 arch_timer_get_rate(void)
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{
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return arch_timer_rate;
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}
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/*
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* Some external users of arch_timer_read_counter (e.g. sched_clock) may try to
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* call it before it has been initialised. Rather than incur a performance
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* penalty checking for initialisation, provide a default implementation that
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* won't lead to time appearing to jump backwards.
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*/
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static u64 arch_timer_read_zero(void)
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{
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return 0;
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}
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u64 (*arch_timer_read_counter)(void) = arch_timer_read_zero;
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static cycle_t arch_counter_read(struct clocksource *cs)
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{
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return arch_timer_read_counter();
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}
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static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
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{
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return arch_timer_read_counter();
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}
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static struct clocksource clocksource_counter = {
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.name = "arch_sys_counter",
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.rating = 400,
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.read = arch_counter_read,
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.mask = CLOCKSOURCE_MASK(56),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static struct cyclecounter cyclecounter = {
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.read = arch_counter_read_cc,
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.mask = CLOCKSOURCE_MASK(56),
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};
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static struct timecounter timecounter;
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struct timecounter *arch_timer_get_timecounter(void)
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{
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return &timecounter;
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}
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static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
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{
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pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
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clk->irq, smp_processor_id());
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if (arch_timer_use_virtual)
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disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
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else {
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disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
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if (arch_timer_ppi[PHYS_NONSECURE_PPI])
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disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
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}
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clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
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}
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static int __cpuinit arch_timer_cpu_notify(struct notifier_block *self,
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unsigned long action, void *hcpu)
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{
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struct clock_event_device *evt = this_cpu_ptr(arch_timer_evt);
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switch (action & ~CPU_TASKS_FROZEN) {
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case CPU_STARTING:
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arch_timer_setup(evt);
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break;
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case CPU_DYING:
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arch_timer_stop(evt);
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block arch_timer_cpu_nb __cpuinitdata = {
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.notifier_call = arch_timer_cpu_notify,
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};
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static int __init arch_timer_register(void)
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{
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int err;
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int ppi;
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err = arch_timer_available();
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if (err)
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goto out;
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arch_timer_evt = alloc_percpu(struct clock_event_device);
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if (!arch_timer_evt) {
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err = -ENOMEM;
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goto out;
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}
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clocksource_register_hz(&clocksource_counter, arch_timer_rate);
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cyclecounter.mult = clocksource_counter.mult;
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cyclecounter.shift = clocksource_counter.shift;
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timecounter_init(&timecounter, &cyclecounter,
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arch_counter_get_cntpct());
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if (arch_timer_use_virtual) {
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ppi = arch_timer_ppi[VIRT_PPI];
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err = request_percpu_irq(ppi, arch_timer_handler_virt,
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"arch_timer", arch_timer_evt);
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} else {
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ppi = arch_timer_ppi[PHYS_SECURE_PPI];
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err = request_percpu_irq(ppi, arch_timer_handler_phys,
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"arch_timer", arch_timer_evt);
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if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
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ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
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err = request_percpu_irq(ppi, arch_timer_handler_phys,
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"arch_timer", arch_timer_evt);
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if (err)
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free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
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arch_timer_evt);
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}
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}
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if (err) {
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pr_err("arch_timer: can't register interrupt %d (%d)\n",
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ppi, err);
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goto out_free;
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}
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err = register_cpu_notifier(&arch_timer_cpu_nb);
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if (err)
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goto out_free_irq;
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/* Immediately configure the timer on the boot CPU */
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arch_timer_setup(this_cpu_ptr(arch_timer_evt));
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return 0;
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out_free_irq:
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if (arch_timer_use_virtual)
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free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
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else {
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free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
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arch_timer_evt);
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if (arch_timer_ppi[PHYS_NONSECURE_PPI])
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free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
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arch_timer_evt);
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}
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out_free:
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free_percpu(arch_timer_evt);
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out:
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return err;
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}
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static const struct of_device_id arch_timer_of_match[] __initconst = {
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{ .compatible = "arm,armv7-timer", },
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{ .compatible = "arm,armv8-timer", },
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{},
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};
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int __init arch_timer_init(void)
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{
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struct device_node *np;
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u32 freq;
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int i;
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np = of_find_matching_node(NULL, arch_timer_of_match);
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if (!np) {
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pr_err("arch_timer: can't find DT node\n");
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return -ENODEV;
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}
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/* Try to determine the frequency from the device tree or CNTFRQ */
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if (!of_property_read_u32(np, "clock-frequency", &freq))
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arch_timer_rate = freq;
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for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
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arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
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of_node_put(np);
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/*
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* If HYP mode is available, we know that the physical timer
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* has been configured to be accessible from PL1. Use it, so
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* that a guest can use the virtual timer instead.
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*
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* If no interrupt provided for virtual timer, we'll have to
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* stick to the physical timer. It'd better be accessible...
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*/
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if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
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arch_timer_use_virtual = false;
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if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
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!arch_timer_ppi[PHYS_NONSECURE_PPI]) {
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pr_warn("arch_timer: No interrupt available, giving up\n");
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return -EINVAL;
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}
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}
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if (arch_timer_use_virtual)
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arch_timer_read_counter = arch_counter_get_cntvct;
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else
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arch_timer_read_counter = arch_counter_get_cntpct;
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return arch_timer_register();
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}
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