300 lines
7.7 KiB
C
300 lines
7.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1997, 1998 Ralf Baechle
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* Copyright (C) 1999 SuSE GmbH
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* Copyright (C) 1999-2001 Hewlett-Packard Company
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* Copyright (C) 1999-2001 Grant Grundler
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*/
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#include <linux/eisa.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <asm/io.h>
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#include <asm/superio.h>
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#define DEBUG_RESOURCES 0
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#define DEBUG_CONFIG 0
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#if DEBUG_CONFIG
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# define DBGC(x...) printk(KERN_DEBUG x)
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#else
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# define DBGC(x...)
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#endif
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#if DEBUG_RESOURCES
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#define DBG_RES(x...) printk(KERN_DEBUG x)
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#else
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#define DBG_RES(x...)
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#endif
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/* To be used as: mdelay(pci_post_reset_delay);
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*
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* post_reset is the time the kernel should stall to prevent anyone from
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* accessing the PCI bus once #RESET is de-asserted.
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* PCI spec somewhere says 1 second but with multi-PCI bus systems,
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* this makes the boot time much longer than necessary.
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* 20ms seems to work for all the HP PCI implementations to date.
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*
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* #define pci_post_reset_delay 50
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*/
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struct pci_port_ops *pci_port __read_mostly;
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struct pci_bios_ops *pci_bios __read_mostly;
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static int pci_hba_count __read_mostly;
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/* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data. */
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#define PCI_HBA_MAX 32
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static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __read_mostly;
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/********************************************************************
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**
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** I/O port space support
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**
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*********************************************************************/
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/* EISA port numbers and PCI port numbers share the same interface. Some
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* machines have both EISA and PCI adapters installed. Rather than turn
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* pci_port into an array, we reserve bus 0 for EISA and call the EISA
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* routines if the access is to a port on bus 0. We don't want to fix
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* EISA and ISA drivers which assume port space is <= 0xffff.
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*/
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#ifdef CONFIG_EISA
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#define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr)
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#define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr)
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#else
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#define EISA_IN(size)
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#define EISA_OUT(size)
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#endif
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#define PCI_PORT_IN(type, size) \
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u##size in##type (int addr) \
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{ \
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int b = PCI_PORT_HBA(addr); \
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EISA_IN(size); \
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if (!parisc_pci_hba[b]) return (u##size) -1; \
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return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \
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} \
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EXPORT_SYMBOL(in##type);
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PCI_PORT_IN(b, 8)
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PCI_PORT_IN(w, 16)
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PCI_PORT_IN(l, 32)
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#define PCI_PORT_OUT(type, size) \
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void out##type (u##size d, int addr) \
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{ \
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int b = PCI_PORT_HBA(addr); \
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EISA_OUT(size); \
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if (!parisc_pci_hba[b]) return; \
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pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \
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} \
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EXPORT_SYMBOL(out##type);
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PCI_PORT_OUT(b, 8)
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PCI_PORT_OUT(w, 16)
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PCI_PORT_OUT(l, 32)
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/*
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* BIOS32 replacement.
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*/
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static int __init pcibios_init(void)
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{
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if (!pci_bios)
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return -1;
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if (pci_bios->init) {
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pci_bios->init();
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} else {
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printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
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}
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/* Set the CLS for PCI as early as possible. */
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pci_cache_line_size = pci_dfl_cache_line_size;
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return 0;
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}
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/* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */
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void pcibios_fixup_bus(struct pci_bus *bus)
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{
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if (pci_bios->fixup_bus) {
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pci_bios->fixup_bus(bus);
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} else {
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printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n");
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}
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}
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/*
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* Called by pci_set_master() - a driver interface.
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*
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* Legacy PDC guarantees to set:
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* Map Memory BAR's into PA IO space.
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* Map Expansion ROM BAR into one common PA IO space per bus.
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* Map IO BAR's into PCI IO space.
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* Command (see below)
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* Cache Line Size
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* Latency Timer
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* Interrupt Line
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* PPB: secondary latency timer, io/mmio base/limit,
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* bus numbers, bridge control
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*
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*/
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void pcibios_set_master(struct pci_dev *dev)
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{
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u8 lat;
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/* If someone already mucked with this, don't touch it. */
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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if (lat >= 16) return;
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/*
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** HP generally has fewer devices on the bus than other architectures.
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** upper byte is PCI_LATENCY_TIMER.
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*/
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pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
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(0x80 << 8) | pci_cache_line_size);
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}
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void __init pcibios_init_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev = bus->self;
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unsigned short bridge_ctl;
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/* We deal only with pci controllers and pci-pci bridges. */
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if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
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return;
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/* PCI-PCI bridge - set the cache line and default latency
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(32) for primary and secondary buses. */
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pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl);
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bridge_ctl |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl);
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}
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/*
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* pcibios align resources() is called every time generic PCI code
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* wants to generate a new address. The process of looking for
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* an available address, each candidate is first "aligned" and
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* then checked if the resource is available until a match is found.
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*
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* Since we are just checking candidates, don't use any fields other
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* than res->start.
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*/
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t alignment)
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{
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resource_size_t mask, align, start = res->start;
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DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n",
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pci_name(((struct pci_dev *) data)),
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res->parent, res->start, res->end,
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(int) res->flags, size, alignment);
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/* If it's not IO, then it's gotta be MEM */
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align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
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/* Align to largest of MIN or input size */
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mask = max(alignment, align) - 1;
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start += mask;
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start &= ~mask;
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return start;
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}
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int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine)
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{
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unsigned long prot;
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/*
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* I/O space can be accessed via normal processor loads and stores on
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* this platform but for now we elect not to do this and portable
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* drivers should not do this anyway.
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*/
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if (mmap_state == pci_mmap_io)
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return -EINVAL;
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if (write_combine)
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return -EINVAL;
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/*
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* Ignore write-combine; for now only return uncached mappings.
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*/
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prot = pgprot_val(vma->vm_page_prot);
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prot |= _PAGE_NO_CACHE;
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vma->vm_page_prot = __pgprot(prot);
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return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
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vma->vm_end - vma->vm_start, vma->vm_page_prot);
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}
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/*
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* A driver is enabling the device. We make sure that all the appropriate
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* bits are set to allow the device to operate as the driver is expecting.
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* We enable the port IO and memory IO bits if the device has any BARs of
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* that type, and we enable the PERR and SERR bits unconditionally.
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* Drivers that do not need parity (eg graphics and possibly networking)
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* can clear these bits if they want.
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*/
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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int err;
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u16 cmd, old_cmd;
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err = pci_enable_resources(dev, mask);
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if (err < 0)
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return err;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
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#if 0
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/* If bridge/bus controller has FBB enabled, child must too. */
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if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
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cmd |= PCI_COMMAND_FAST_BACK;
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#endif
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if (cmd != old_cmd) {
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dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n",
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old_cmd, cmd);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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/* PA-RISC specific */
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void pcibios_register_hba(struct pci_hba_data *hba)
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{
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if (pci_hba_count >= PCI_HBA_MAX) {
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printk(KERN_ERR "PCI: Too many Host Bus Adapters\n");
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return;
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}
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parisc_pci_hba[pci_hba_count] = hba;
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hba->hba_num = pci_hba_count++;
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}
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subsys_initcall(pcibios_init);
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