1216 lines
32 KiB
ArmAsm
1216 lines
32 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Adapted for Power Macintosh by Paul Mackerras.
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* Low-level exception handlers and MMU support
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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* MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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*
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* This file contains the low-level support and setup for the
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* PowerPC platform, including trap and interrupt dispatch.
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* (The PPC 8xx embedded CPUs use head_8xx.S instead.)
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*/
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#include <linux/init.h>
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#include <linux/pgtable.h>
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#include <linux/linkage.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/cputable.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/ptrace.h>
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#include <asm/bug.h>
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#include <asm/kvm_book3s_asm.h>
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#include <asm/export.h>
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#include <asm/feature-fixups.h>
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#include <asm/interrupt.h>
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#include "head_32.h"
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#define LOAD_BAT(n, reg, RA, RB) \
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/* see the comment for clear_bats() -- Cort */ \
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li RA,0; \
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mtspr SPRN_IBAT##n##U,RA; \
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mtspr SPRN_DBAT##n##U,RA; \
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lwz RA,(n*16)+0(reg); \
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lwz RB,(n*16)+4(reg); \
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mtspr SPRN_IBAT##n##U,RA; \
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mtspr SPRN_IBAT##n##L,RB; \
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lwz RA,(n*16)+8(reg); \
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lwz RB,(n*16)+12(reg); \
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mtspr SPRN_DBAT##n##U,RA; \
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mtspr SPRN_DBAT##n##L,RB
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__HEAD
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_GLOBAL(_stext);
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/*
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* _start is defined this way because the XCOFF loader in the OpenFirmware
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* on the powermac expects the entry point to be a procedure descriptor.
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*/
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_GLOBAL(_start);
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/*
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* These are here for legacy reasons, the kernel used to
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* need to look like a coff function entry for the pmac
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* but we're always started by some kind of bootloader now.
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* -- Cort
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*/
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nop /* used by __secondary_hold on prep (mtx) and chrp smp */
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nop /* used by __secondary_hold on prep (mtx) and chrp smp */
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nop
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/* PMAC
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* Enter here with the kernel text, data and bss loaded starting at
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* 0, running with virtual == physical mapping.
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* r5 points to the prom entry point (the client interface handler
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* address). Address translation is turned on, with the prom
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* managing the hash table. Interrupts are disabled. The stack
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* pointer (r1) points to just below the end of the half-meg region
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* from 0x380000 - 0x400000, which is mapped in already.
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*
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* If we are booted from MacOS via BootX, we enter with the kernel
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* image loaded somewhere, and the following values in registers:
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* r3: 'BooX' (0x426f6f58)
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* r4: virtual address of boot_infos_t
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* r5: 0
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*
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* PREP
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* This is jumped to on prep systems right after the kernel is relocated
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* to its proper place in memory by the boot loader. The expected layout
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* of the regs is:
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* r3: ptr to residual data
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* r4: initrd_start or if no initrd then 0
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* r5: initrd_end - unused if r4 is 0
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* r6: Start of command line string
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* r7: End of command line string
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*
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* This just gets a minimal mmu environment setup so we can call
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* start_here() to do the real work.
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* -- Cort
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*/
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.globl __start
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__start:
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/*
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* We have to do any OF calls before we map ourselves to KERNELBASE,
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* because OF may have I/O devices mapped into that area
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* (particularly on CHRP).
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*/
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cmpwi 0,r5,0
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beq 1f
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#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
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/* find out where we are now */
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bcl 20,31,$+4
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0: mflr r8 /* r8 = runtime addr here */
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addis r8,r8,(_stext - 0b)@ha
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addi r8,r8,(_stext - 0b)@l /* current runtime base addr */
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bl prom_init
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#endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
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/* We never return. We also hit that trap if trying to boot
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* from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
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trap
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/*
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* Check for BootX signature when supporting PowerMac and branch to
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* appropriate trampoline if it's present
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*/
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#ifdef CONFIG_PPC_PMAC
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1: lis r31,0x426f
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ori r31,r31,0x6f58
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cmpw 0,r3,r31
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bne 1f
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bl bootx_init
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trap
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#endif /* CONFIG_PPC_PMAC */
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1: mr r31,r3 /* save device tree ptr */
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li r24,0 /* cpu # */
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/*
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* early_init() does the early machine identification and does
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* the necessary low-level setup and clears the BSS
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* -- Cort <cort@fsmlabs.com>
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*/
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bl early_init
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/* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
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* the physical address we are running at, returned by early_init()
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*/
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bl mmu_off
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__after_mmu_off:
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bl clear_bats
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bl flush_tlbs
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bl initial_bats
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bl load_segment_registers
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bl reloc_offset
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bl early_hash_table
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#if defined(CONFIG_BOOTX_TEXT)
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bl setup_disp_bat
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#endif
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#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
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bl setup_cpm_bat
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#endif
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#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
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bl setup_usbgecko_bat
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#endif
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/*
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* Call setup_cpu for CPU 0 and initialize 6xx Idle
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*/
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bl reloc_offset
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li r24,0 /* cpu# */
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bl call_setup_cpu /* Call setup_cpu for this CPU */
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bl reloc_offset
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bl init_idle_6xx
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/*
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* We need to run with _start at physical address 0.
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* On CHRP, we are loaded at 0x10000 since OF on CHRP uses
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* the exception vectors at 0 (and therefore this copy
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* overwrites OF's exception vectors with our own).
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* The MMU is off at this point.
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*/
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bl reloc_offset
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mr r26,r3
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addis r4,r3,KERNELBASE@h /* current address of _start */
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lis r5,PHYSICAL_START@h
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cmplw 0,r4,r5 /* already running at PHYSICAL_START? */
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bne relocate_kernel
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/*
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* we now have the 1st 16M of ram mapped with the bats.
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* prep needs the mmu to be turned on here, but pmac already has it on.
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* this shouldn't bother the pmac since it just gets turned on again
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* as we jump to our code at KERNELBASE. -- Cort
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* Actually no, pmac doesn't have it on any more. BootX enters with MMU
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* off, and in other cases, we now turn it off before changing BATs above.
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*/
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turn_on_mmu:
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mfmsr r0
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ori r0,r0,MSR_DR|MSR_IR|MSR_RI
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mtspr SPRN_SRR1,r0
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lis r0,start_here@h
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ori r0,r0,start_here@l
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mtspr SPRN_SRR0,r0
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rfi /* enables MMU */
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/*
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* We need __secondary_hold as a place to hold the other cpus on
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* an SMP machine, even when we are running a UP kernel.
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*/
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. = 0xc0 /* for prep bootloader */
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li r3,1 /* MTX only has 1 cpu */
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.globl __secondary_hold
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__secondary_hold:
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/* tell the master we're here */
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stw r3,__secondary_hold_acknowledge@l(0)
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#ifdef CONFIG_SMP
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100: lwz r4,0(0)
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/* wait until we're told to start */
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cmpw 0,r4,r3
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bne 100b
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/* our cpu # was at addr 0 - go */
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mr r24,r3 /* cpu # */
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b __secondary_start
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#else
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b .
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#endif /* CONFIG_SMP */
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.globl __secondary_hold_spinloop
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__secondary_hold_spinloop:
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.long 0
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.globl __secondary_hold_acknowledge
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__secondary_hold_acknowledge:
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.long -1
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/* System reset */
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/* core99 pmac starts the seconary here by changing the vector, and
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putting it back to what it was (unknown_async_exception) when done. */
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EXCEPTION(INTERRUPT_SYSTEM_RESET, Reset, unknown_async_exception)
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/* Machine check */
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/*
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* On CHRP, this is complicated by the fact that we could get a
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* machine check inside RTAS, and we have no guarantee that certain
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* critical registers will have the values we expect. The set of
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* registers that might have bad values includes all the GPRs
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* and all the BATs. We indicate that we are in RTAS by putting
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* a non-zero value, the address of the exception frame to use,
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* in thread.rtas_sp. The machine check handler checks thread.rtas_sp
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* and uses its value if it is non-zero.
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* (Other exception handlers assume that r1 is a valid kernel stack
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* pointer when we take an exception from supervisor mode.)
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* -- paulus.
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*/
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START_EXCEPTION(INTERRUPT_MACHINE_CHECK, MachineCheck)
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EXCEPTION_PROLOG_0
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#ifdef CONFIG_PPC_CHRP
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mtspr SPRN_SPRG_SCRATCH2,r1
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mfspr r1, SPRN_SPRG_THREAD
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lwz r1, RTAS_SP(r1)
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cmpwi cr1, r1, 0
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bne cr1, 7f
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mfspr r1, SPRN_SPRG_SCRATCH2
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#endif /* CONFIG_PPC_CHRP */
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EXCEPTION_PROLOG_1
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7: EXCEPTION_PROLOG_2 0x200 MachineCheck
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#ifdef CONFIG_PPC_CHRP
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beq cr1, 1f
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twi 31, 0, 0
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#endif
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1: prepare_transfer_to_handler
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bl machine_check_exception
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b interrupt_return
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/* Data access exception. */
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START_EXCEPTION(INTERRUPT_DATA_STORAGE, DataAccess)
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#ifdef CONFIG_PPC_BOOK3S_604
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BEGIN_MMU_FTR_SECTION
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mtspr SPRN_SPRG_SCRATCH2,r10
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mfspr r10, SPRN_SPRG_THREAD
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stw r11, THR11(r10)
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mfspr r10, SPRN_DSISR
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mfcr r11
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andis. r10, r10, (DSISR_BAD_FAULT_32S | DSISR_DABRMATCH)@h
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mfspr r10, SPRN_SPRG_THREAD
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beq hash_page_dsi
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.Lhash_page_dsi_cont:
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mtcr r11
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lwz r11, THR11(r10)
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mfspr r10, SPRN_SPRG_SCRATCH2
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MMU_FTR_SECTION_ELSE
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b 1f
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ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)
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#endif
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1: EXCEPTION_PROLOG_0 handle_dar_dsisr=1
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EXCEPTION_PROLOG_1
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EXCEPTION_PROLOG_2 INTERRUPT_DATA_STORAGE DataAccess handle_dar_dsisr=1
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prepare_transfer_to_handler
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lwz r5, _DSISR(r1)
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andis. r0, r5, DSISR_DABRMATCH@h
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bne- 1f
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bl do_page_fault
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b interrupt_return
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1: bl do_break
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REST_NVGPRS(r1)
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b interrupt_return
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/* Instruction access exception. */
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START_EXCEPTION(INTERRUPT_INST_STORAGE, InstructionAccess)
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mtspr SPRN_SPRG_SCRATCH0,r10
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mtspr SPRN_SPRG_SCRATCH1,r11
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mfspr r10, SPRN_SPRG_THREAD
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mfspr r11, SPRN_SRR0
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stw r11, SRR0(r10)
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mfspr r11, SPRN_SRR1 /* check whether user or kernel */
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stw r11, SRR1(r10)
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mfcr r10
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#ifdef CONFIG_PPC_BOOK3S_604
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BEGIN_MMU_FTR_SECTION
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andis. r11, r11, SRR1_ISI_NOPT@h /* no pte found? */
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bne hash_page_isi
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.Lhash_page_isi_cont:
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mfspr r11, SPRN_SRR1 /* check whether user or kernel */
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
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#endif
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andi. r11, r11, MSR_PR
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EXCEPTION_PROLOG_1
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EXCEPTION_PROLOG_2 INTERRUPT_INST_STORAGE InstructionAccess
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andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
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stw r5, _DSISR(r11)
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stw r12, _DAR(r11)
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prepare_transfer_to_handler
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bl do_page_fault
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b interrupt_return
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/* External interrupt */
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EXCEPTION(INTERRUPT_EXTERNAL, HardwareInterrupt, do_IRQ)
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/* Alignment exception */
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START_EXCEPTION(INTERRUPT_ALIGNMENT, Alignment)
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EXCEPTION_PROLOG INTERRUPT_ALIGNMENT Alignment handle_dar_dsisr=1
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prepare_transfer_to_handler
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bl alignment_exception
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REST_NVGPRS(r1)
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b interrupt_return
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/* Program check exception */
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START_EXCEPTION(INTERRUPT_PROGRAM, ProgramCheck)
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EXCEPTION_PROLOG INTERRUPT_PROGRAM ProgramCheck
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prepare_transfer_to_handler
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bl program_check_exception
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REST_NVGPRS(r1)
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b interrupt_return
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/* Floating-point unavailable */
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START_EXCEPTION(0x800, FPUnavailable)
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#ifdef CONFIG_PPC_FPU
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BEGIN_FTR_SECTION
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/*
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* Certain Freescale cores don't have a FPU and treat fp instructions
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* as a FP Unavailable exception. Redirect to illegal/emulation handling.
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*/
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b ProgramCheck
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END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
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EXCEPTION_PROLOG INTERRUPT_FP_UNAVAIL FPUnavailable
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beq 1f
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bl load_up_fpu /* if from user, just load it up */
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b fast_exception_return
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1: prepare_transfer_to_handler
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bl kernel_fp_unavailable_exception
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b interrupt_return
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#else
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b ProgramCheck
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#endif
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/* Decrementer */
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EXCEPTION(INTERRUPT_DECREMENTER, Decrementer, timer_interrupt)
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EXCEPTION(0xa00, Trap_0a, unknown_exception)
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EXCEPTION(0xb00, Trap_0b, unknown_exception)
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/* System call */
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START_EXCEPTION(INTERRUPT_SYSCALL, SystemCall)
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SYSCALL_ENTRY INTERRUPT_SYSCALL
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EXCEPTION(INTERRUPT_TRACE, SingleStep, single_step_exception)
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EXCEPTION(0xe00, Trap_0e, unknown_exception)
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/*
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* The Altivec unavailable trap is at 0x0f20. Foo.
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* We effectively remap it to 0x3000.
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* We include an altivec unavailable exception vector even if
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* not configured for Altivec, so that you can't panic a
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* non-altivec kernel running on a machine with altivec just
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* by executing an altivec instruction.
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*/
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START_EXCEPTION(INTERRUPT_PERFMON, PerformanceMonitorTrap)
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b PerformanceMonitor
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START_EXCEPTION(INTERRUPT_ALTIVEC_UNAVAIL, AltiVecUnavailableTrap)
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b AltiVecUnavailable
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__HEAD
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/*
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* Handle TLB miss for instruction on 603/603e.
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* Note: we get an alternate set of r0 - r3 to use automatically.
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*/
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. = INTERRUPT_INST_TLB_MISS_603
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InstructionTLBMiss:
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/*
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* r0: scratch
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* r1: linux style pte ( later becomes ppc hardware pte )
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* r2: ptr to linux-style pte
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* r3: scratch
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*/
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/* Get PTE (linux-style) and check access */
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mfspr r3,SPRN_IMISS
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#ifdef CONFIG_MODULES
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lis r1, TASK_SIZE@h /* check if kernel address */
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cmplw 0,r1,r3
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#endif
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mfspr r2, SPRN_SDR1
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li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC | _PAGE_USER
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rlwinm r2, r2, 28, 0xfffff000
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#ifdef CONFIG_MODULES
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bgt- 112f
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lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
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li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
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addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
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#endif
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112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
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lwz r2,0(r2) /* get pmd entry */
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rlwinm. r2,r2,0,0,19 /* extract address of pte page */
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beq- InstructionAddressInvalid /* return if no mapping */
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rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
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lwz r0,0(r2) /* get linux-style pte */
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andc. r1,r1,r0 /* check access & ~permission */
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bne- InstructionAddressInvalid /* return if access not permitted */
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/* Convert linux-style PTE to low word of PPC-style PTE */
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rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
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ori r1, r1, 0xe06 /* clear out reserved bits */
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andc r1, r0, r1 /* PP = user? 1 : 0 */
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BEGIN_FTR_SECTION
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rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
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END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
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mtspr SPRN_RPA,r1
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tlbli r3
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mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
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mtcrf 0x80,r3
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rfi
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InstructionAddressInvalid:
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mfspr r3,SPRN_SRR1
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rlwinm r1,r3,9,6,6 /* Get load/store bit */
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addis r1,r1,0x2000
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mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
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andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
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or r2,r2,r1
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|
mtspr SPRN_SRR1,r2
|
|
mfspr r1,SPRN_IMISS /* Get failing address */
|
|
rlwinm. r2,r2,0,31,31 /* Check for little endian access */
|
|
rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
|
|
xor r1,r1,r2
|
|
mtspr SPRN_DAR,r1 /* Set fault address */
|
|
mfmsr r0 /* Restore "normal" registers */
|
|
xoris r0,r0,MSR_TGPR>>16
|
|
mtcrf 0x80,r3 /* Restore CR0 */
|
|
mtmsr r0
|
|
b InstructionAccess
|
|
|
|
/*
|
|
* Handle TLB miss for DATA Load operation on 603/603e
|
|
*/
|
|
. = INTERRUPT_DATA_LOAD_TLB_MISS_603
|
|
DataLoadTLBMiss:
|
|
/*
|
|
* r0: scratch
|
|
* r1: linux style pte ( later becomes ppc hardware pte )
|
|
* r2: ptr to linux-style pte
|
|
* r3: scratch
|
|
*/
|
|
/* Get PTE (linux-style) and check access */
|
|
mfspr r3,SPRN_DMISS
|
|
lis r1, TASK_SIZE@h /* check if kernel address */
|
|
cmplw 0,r1,r3
|
|
mfspr r2, SPRN_SDR1
|
|
li r1, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER
|
|
rlwinm r2, r2, 28, 0xfffff000
|
|
bgt- 112f
|
|
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
|
|
li r1, _PAGE_PRESENT | _PAGE_ACCESSED
|
|
addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
|
|
112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
|
|
lwz r2,0(r2) /* get pmd entry */
|
|
rlwinm. r2,r2,0,0,19 /* extract address of pte page */
|
|
beq- DataAddressInvalid /* return if no mapping */
|
|
rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
|
|
lwz r0,0(r2) /* get linux-style pte */
|
|
andc. r1,r1,r0 /* check access & ~permission */
|
|
bne- DataAddressInvalid /* return if access not permitted */
|
|
/* Convert linux-style PTE to low word of PPC-style PTE */
|
|
rlwinm r1,r0,32-9,30,30 /* _PAGE_RW -> PP msb */
|
|
rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
|
|
rlwimi r1,r0,32-3,24,24 /* _PAGE_RW -> _PAGE_DIRTY */
|
|
rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
|
|
xori r1,r1,_PAGE_DIRTY /* clear dirty when not rw */
|
|
ori r1,r1,0xe04 /* clear out reserved bits */
|
|
andc r1,r0,r1 /* PP = user? rw? 1: 3: 0 */
|
|
BEGIN_FTR_SECTION
|
|
rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
|
|
END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
|
|
mtspr SPRN_RPA,r1
|
|
BEGIN_MMU_FTR_SECTION
|
|
li r0,1
|
|
mfspr r1,SPRN_SPRG_603_LRU
|
|
rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
|
|
slw r0,r0,r2
|
|
xor r1,r0,r1
|
|
srw r0,r1,r2
|
|
mtspr SPRN_SPRG_603_LRU,r1
|
|
mfspr r2,SPRN_SRR1
|
|
rlwimi r2,r0,31-14,14,14
|
|
mtspr SPRN_SRR1,r2
|
|
mtcrf 0x80,r2
|
|
tlbld r3
|
|
rfi
|
|
MMU_FTR_SECTION_ELSE
|
|
mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
|
|
mtcrf 0x80,r2
|
|
tlbld r3
|
|
rfi
|
|
ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
|
|
DataAddressInvalid:
|
|
mfspr r3,SPRN_SRR1
|
|
rlwinm r1,r3,9,6,6 /* Get load/store bit */
|
|
addis r1,r1,0x2000
|
|
mtspr SPRN_DSISR,r1
|
|
andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
|
|
mtspr SPRN_SRR1,r2
|
|
mfspr r1,SPRN_DMISS /* Get failing address */
|
|
rlwinm. r2,r2,0,31,31 /* Check for little endian access */
|
|
beq 20f /* Jump if big endian */
|
|
xori r1,r1,3
|
|
20: mtspr SPRN_DAR,r1 /* Set fault address */
|
|
mfmsr r0 /* Restore "normal" registers */
|
|
xoris r0,r0,MSR_TGPR>>16
|
|
mtcrf 0x80,r3 /* Restore CR0 */
|
|
mtmsr r0
|
|
b DataAccess
|
|
|
|
/*
|
|
* Handle TLB miss for DATA Store on 603/603e
|
|
*/
|
|
. = INTERRUPT_DATA_STORE_TLB_MISS_603
|
|
DataStoreTLBMiss:
|
|
/*
|
|
* r0: scratch
|
|
* r1: linux style pte ( later becomes ppc hardware pte )
|
|
* r2: ptr to linux-style pte
|
|
* r3: scratch
|
|
*/
|
|
/* Get PTE (linux-style) and check access */
|
|
mfspr r3,SPRN_DMISS
|
|
lis r1, TASK_SIZE@h /* check if kernel address */
|
|
cmplw 0,r1,r3
|
|
mfspr r2, SPRN_SDR1
|
|
li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER
|
|
rlwinm r2, r2, 28, 0xfffff000
|
|
bgt- 112f
|
|
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
|
|
li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED
|
|
addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
|
|
112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
|
|
lwz r2,0(r2) /* get pmd entry */
|
|
rlwinm. r2,r2,0,0,19 /* extract address of pte page */
|
|
beq- DataAddressInvalid /* return if no mapping */
|
|
rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
|
|
lwz r0,0(r2) /* get linux-style pte */
|
|
andc. r1,r1,r0 /* check access & ~permission */
|
|
bne- DataAddressInvalid /* return if access not permitted */
|
|
/* Convert linux-style PTE to low word of PPC-style PTE */
|
|
rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
|
|
li r1,0xe06 /* clear out reserved bits & PP msb */
|
|
andc r1,r0,r1 /* PP = user? 1: 0 */
|
|
BEGIN_FTR_SECTION
|
|
rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
|
|
END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
|
|
mtspr SPRN_RPA,r1
|
|
mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
|
|
mtcrf 0x80,r2
|
|
BEGIN_MMU_FTR_SECTION
|
|
li r0,1
|
|
mfspr r1,SPRN_SPRG_603_LRU
|
|
rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
|
|
slw r0,r0,r2
|
|
xor r1,r0,r1
|
|
srw r0,r1,r2
|
|
mtspr SPRN_SPRG_603_LRU,r1
|
|
mfspr r2,SPRN_SRR1
|
|
rlwimi r2,r0,31-14,14,14
|
|
mtspr SPRN_SRR1,r2
|
|
mtcrf 0x80,r2
|
|
tlbld r3
|
|
rfi
|
|
MMU_FTR_SECTION_ELSE
|
|
mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
|
|
mtcrf 0x80,r2
|
|
tlbld r3
|
|
rfi
|
|
ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
|
|
|
|
#ifndef CONFIG_ALTIVEC
|
|
#define altivec_assist_exception unknown_exception
|
|
#endif
|
|
|
|
#ifndef CONFIG_TAU_INT
|
|
#define TAUException unknown_async_exception
|
|
#endif
|
|
|
|
EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception)
|
|
EXCEPTION(0x1400, SMI, SMIException)
|
|
EXCEPTION(0x1500, Trap_15, unknown_exception)
|
|
EXCEPTION(0x1600, Trap_16, altivec_assist_exception)
|
|
EXCEPTION(0x1700, Trap_17, TAUException)
|
|
EXCEPTION(0x1800, Trap_18, unknown_exception)
|
|
EXCEPTION(0x1900, Trap_19, unknown_exception)
|
|
EXCEPTION(0x1a00, Trap_1a, unknown_exception)
|
|
EXCEPTION(0x1b00, Trap_1b, unknown_exception)
|
|
EXCEPTION(0x1c00, Trap_1c, unknown_exception)
|
|
EXCEPTION(0x1d00, Trap_1d, unknown_exception)
|
|
EXCEPTION(0x1e00, Trap_1e, unknown_exception)
|
|
EXCEPTION(0x1f00, Trap_1f, unknown_exception)
|
|
EXCEPTION(0x2000, RunMode, RunModeException)
|
|
EXCEPTION(0x2100, Trap_21, unknown_exception)
|
|
EXCEPTION(0x2200, Trap_22, unknown_exception)
|
|
EXCEPTION(0x2300, Trap_23, unknown_exception)
|
|
EXCEPTION(0x2400, Trap_24, unknown_exception)
|
|
EXCEPTION(0x2500, Trap_25, unknown_exception)
|
|
EXCEPTION(0x2600, Trap_26, unknown_exception)
|
|
EXCEPTION(0x2700, Trap_27, unknown_exception)
|
|
EXCEPTION(0x2800, Trap_28, unknown_exception)
|
|
EXCEPTION(0x2900, Trap_29, unknown_exception)
|
|
EXCEPTION(0x2a00, Trap_2a, unknown_exception)
|
|
EXCEPTION(0x2b00, Trap_2b, unknown_exception)
|
|
EXCEPTION(0x2c00, Trap_2c, unknown_exception)
|
|
EXCEPTION(0x2d00, Trap_2d, unknown_exception)
|
|
EXCEPTION(0x2e00, Trap_2e, unknown_exception)
|
|
EXCEPTION(0x2f00, Trap_2f, unknown_exception)
|
|
|
|
__HEAD
|
|
. = 0x3000
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S_604
|
|
.macro save_regs_thread thread
|
|
stw r0, THR0(\thread)
|
|
stw r3, THR3(\thread)
|
|
stw r4, THR4(\thread)
|
|
stw r5, THR5(\thread)
|
|
stw r6, THR6(\thread)
|
|
stw r8, THR8(\thread)
|
|
stw r9, THR9(\thread)
|
|
mflr r0
|
|
stw r0, THLR(\thread)
|
|
mfctr r0
|
|
stw r0, THCTR(\thread)
|
|
.endm
|
|
|
|
.macro restore_regs_thread thread
|
|
lwz r0, THLR(\thread)
|
|
mtlr r0
|
|
lwz r0, THCTR(\thread)
|
|
mtctr r0
|
|
lwz r0, THR0(\thread)
|
|
lwz r3, THR3(\thread)
|
|
lwz r4, THR4(\thread)
|
|
lwz r5, THR5(\thread)
|
|
lwz r6, THR6(\thread)
|
|
lwz r8, THR8(\thread)
|
|
lwz r9, THR9(\thread)
|
|
.endm
|
|
|
|
hash_page_dsi:
|
|
save_regs_thread r10
|
|
mfdsisr r3
|
|
mfdar r4
|
|
mfsrr0 r5
|
|
mfsrr1 r9
|
|
rlwinm r3, r3, 32 - 15, _PAGE_RW /* DSISR_STORE -> _PAGE_RW */
|
|
bl hash_page
|
|
mfspr r10, SPRN_SPRG_THREAD
|
|
restore_regs_thread r10
|
|
b .Lhash_page_dsi_cont
|
|
|
|
hash_page_isi:
|
|
mr r11, r10
|
|
mfspr r10, SPRN_SPRG_THREAD
|
|
save_regs_thread r10
|
|
li r3, 0
|
|
lwz r4, SRR0(r10)
|
|
lwz r9, SRR1(r10)
|
|
bl hash_page
|
|
mfspr r10, SPRN_SPRG_THREAD
|
|
restore_regs_thread r10
|
|
mr r10, r11
|
|
b .Lhash_page_isi_cont
|
|
|
|
.globl fast_hash_page_return
|
|
fast_hash_page_return:
|
|
andis. r10, r9, SRR1_ISI_NOPT@h /* Set on ISI, cleared on DSI */
|
|
mfspr r10, SPRN_SPRG_THREAD
|
|
restore_regs_thread r10
|
|
bne 1f
|
|
|
|
/* DSI */
|
|
mtcr r11
|
|
lwz r11, THR11(r10)
|
|
mfspr r10, SPRN_SPRG_SCRATCH2
|
|
rfi
|
|
|
|
1: /* ISI */
|
|
mtcr r11
|
|
mfspr r11, SPRN_SPRG_SCRATCH1
|
|
mfspr r10, SPRN_SPRG_SCRATCH0
|
|
rfi
|
|
#endif /* CONFIG_PPC_BOOK3S_604 */
|
|
|
|
#ifdef CONFIG_VMAP_STACK
|
|
vmap_stack_overflow_exception
|
|
#endif
|
|
|
|
__HEAD
|
|
AltiVecUnavailable:
|
|
EXCEPTION_PROLOG 0xf20 AltiVecUnavailable
|
|
#ifdef CONFIG_ALTIVEC
|
|
beq 1f
|
|
bl load_up_altivec /* if from user, just load it up */
|
|
b fast_exception_return
|
|
#endif /* CONFIG_ALTIVEC */
|
|
1: prepare_transfer_to_handler
|
|
bl altivec_unavailable_exception
|
|
b interrupt_return
|
|
|
|
__HEAD
|
|
PerformanceMonitor:
|
|
EXCEPTION_PROLOG 0xf00 PerformanceMonitor
|
|
prepare_transfer_to_handler
|
|
bl performance_monitor_exception
|
|
b interrupt_return
|
|
|
|
|
|
__HEAD
|
|
/*
|
|
* This code is jumped to from the startup code to copy
|
|
* the kernel image to physical address PHYSICAL_START.
|
|
*/
|
|
relocate_kernel:
|
|
lis r3,PHYSICAL_START@h /* Destination base address */
|
|
li r6,0 /* Destination offset */
|
|
li r5,0x4000 /* # bytes of memory to copy */
|
|
bl copy_and_flush /* copy the first 0x4000 bytes */
|
|
addi r0,r3,4f@l /* jump to the address of 4f */
|
|
mtctr r0 /* in copy and do the rest. */
|
|
bctr /* jump to the copy */
|
|
4: lis r5,_end-KERNELBASE@h
|
|
ori r5,r5,_end-KERNELBASE@l
|
|
bl copy_and_flush /* copy the rest */
|
|
b turn_on_mmu
|
|
|
|
/*
|
|
* Copy routine used to copy the kernel to start at physical address 0
|
|
* and flush and invalidate the caches as needed.
|
|
* r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
|
|
* on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
|
|
*/
|
|
_GLOBAL(copy_and_flush)
|
|
addi r5,r5,-4
|
|
addi r6,r6,-4
|
|
4: li r0,L1_CACHE_BYTES/4
|
|
mtctr r0
|
|
3: addi r6,r6,4 /* copy a cache line */
|
|
lwzx r0,r6,r4
|
|
stwx r0,r6,r3
|
|
bdnz 3b
|
|
dcbst r6,r3 /* write it to memory */
|
|
sync
|
|
icbi r6,r3 /* flush the icache line */
|
|
cmplw 0,r6,r5
|
|
blt 4b
|
|
sync /* additional sync needed on g4 */
|
|
isync
|
|
addi r5,r5,4
|
|
addi r6,r6,4
|
|
blr
|
|
|
|
#ifdef CONFIG_SMP
|
|
.globl __secondary_start_mpc86xx
|
|
__secondary_start_mpc86xx:
|
|
mfspr r3, SPRN_PIR
|
|
stw r3, __secondary_hold_acknowledge@l(0)
|
|
mr r24, r3 /* cpu # */
|
|
b __secondary_start
|
|
|
|
.globl __secondary_start_pmac_0
|
|
__secondary_start_pmac_0:
|
|
/* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
|
|
li r24,0
|
|
b 1f
|
|
li r24,1
|
|
b 1f
|
|
li r24,2
|
|
b 1f
|
|
li r24,3
|
|
1:
|
|
/* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
|
|
set to map the 0xf0000000 - 0xffffffff region */
|
|
mfmsr r0
|
|
rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
|
|
mtmsr r0
|
|
isync
|
|
|
|
.globl __secondary_start
|
|
__secondary_start:
|
|
/* Copy some CPU settings from CPU 0 */
|
|
bl __restore_cpu_setup
|
|
|
|
lis r3,-KERNELBASE@h
|
|
mr r4,r24
|
|
bl call_setup_cpu /* Call setup_cpu for this CPU */
|
|
lis r3,-KERNELBASE@h
|
|
bl init_idle_6xx
|
|
|
|
/* get current's stack and current */
|
|
lis r2,secondary_current@ha
|
|
tophys(r2,r2)
|
|
lwz r2,secondary_current@l(r2)
|
|
tophys(r1,r2)
|
|
lwz r1,TASK_STACK(r1)
|
|
|
|
/* stack */
|
|
addi r1,r1,THREAD_SIZE-STACK_FRAME_MIN_SIZE
|
|
li r0,0
|
|
tophys(r3,r1)
|
|
stw r0,0(r3)
|
|
|
|
/* load up the MMU */
|
|
bl load_segment_registers
|
|
bl load_up_mmu
|
|
|
|
/* ptr to phys current thread */
|
|
tophys(r4,r2)
|
|
addi r4,r4,THREAD /* phys address of our thread_struct */
|
|
mtspr SPRN_SPRG_THREAD,r4
|
|
BEGIN_MMU_FTR_SECTION
|
|
lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
|
|
ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
|
|
rlwinm r4, r4, 4, 0xffff01ff
|
|
mtspr SPRN_SDR1, r4
|
|
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_HPTE_TABLE)
|
|
|
|
/* enable MMU and jump to start_secondary */
|
|
li r4,MSR_KERNEL
|
|
lis r3,start_secondary@h
|
|
ori r3,r3,start_secondary@l
|
|
mtspr SPRN_SRR0,r3
|
|
mtspr SPRN_SRR1,r4
|
|
rfi
|
|
#endif /* CONFIG_SMP */
|
|
|
|
#ifdef CONFIG_KVM_BOOK3S_HANDLER
|
|
#include "../kvm/book3s_rmhandlers.S"
|
|
#endif
|
|
|
|
/*
|
|
* Load stuff into the MMU. Intended to be called with
|
|
* IR=0 and DR=0.
|
|
*/
|
|
SYM_FUNC_START_LOCAL(early_hash_table)
|
|
sync /* Force all PTE updates to finish */
|
|
isync
|
|
tlbia /* Clear all TLB entries */
|
|
sync /* wait for tlbia/tlbie to finish */
|
|
TLBSYNC /* ... on all CPUs */
|
|
/* Load the SDR1 register (hash table base & size) */
|
|
lis r6, early_hash - PAGE_OFFSET@h
|
|
ori r6, r6, 3 /* 256kB table */
|
|
mtspr SPRN_SDR1, r6
|
|
blr
|
|
SYM_FUNC_END(early_hash_table)
|
|
|
|
SYM_FUNC_START_LOCAL(load_up_mmu)
|
|
sync /* Force all PTE updates to finish */
|
|
isync
|
|
tlbia /* Clear all TLB entries */
|
|
sync /* wait for tlbia/tlbie to finish */
|
|
TLBSYNC /* ... on all CPUs */
|
|
BEGIN_MMU_FTR_SECTION
|
|
/* Load the SDR1 register (hash table base & size) */
|
|
lis r6,_SDR1@ha
|
|
tophys(r6,r6)
|
|
lwz r6,_SDR1@l(r6)
|
|
mtspr SPRN_SDR1,r6
|
|
END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
|
|
|
|
/* Load the BAT registers with the values set up by MMU_init. */
|
|
lis r3,BATS@ha
|
|
addi r3,r3,BATS@l
|
|
tophys(r3,r3)
|
|
LOAD_BAT(0,r3,r4,r5)
|
|
LOAD_BAT(1,r3,r4,r5)
|
|
LOAD_BAT(2,r3,r4,r5)
|
|
LOAD_BAT(3,r3,r4,r5)
|
|
BEGIN_MMU_FTR_SECTION
|
|
LOAD_BAT(4,r3,r4,r5)
|
|
LOAD_BAT(5,r3,r4,r5)
|
|
LOAD_BAT(6,r3,r4,r5)
|
|
LOAD_BAT(7,r3,r4,r5)
|
|
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
|
|
blr
|
|
SYM_FUNC_END(load_up_mmu)
|
|
|
|
_GLOBAL(load_segment_registers)
|
|
li r0, NUM_USER_SEGMENTS /* load up user segment register values */
|
|
mtctr r0 /* for context 0 */
|
|
#ifdef CONFIG_PPC_KUEP
|
|
lis r3, SR_NX@h /* Kp = 0, Ks = 0, VSID = 0 */
|
|
#else
|
|
li r3, 0 /* Kp = 0, Ks = 0, VSID = 0 */
|
|
#endif
|
|
li r4, 0
|
|
3: mtsrin r3, r4
|
|
addi r3, r3, 0x111 /* increment VSID */
|
|
addis r4, r4, 0x1000 /* address of next segment */
|
|
bdnz 3b
|
|
li r0, 16 - NUM_USER_SEGMENTS /* load up kernel segment registers */
|
|
mtctr r0 /* for context 0 */
|
|
rlwinm r3, r3, 0, ~SR_NX /* Nx = 0 */
|
|
rlwinm r3, r3, 0, ~SR_KS /* Ks = 0 */
|
|
oris r3, r3, SR_KP@h /* Kp = 1 */
|
|
3: mtsrin r3, r4
|
|
addi r3, r3, 0x111 /* increment VSID */
|
|
addis r4, r4, 0x1000 /* address of next segment */
|
|
bdnz 3b
|
|
blr
|
|
|
|
/*
|
|
* This is where the main kernel code starts.
|
|
*/
|
|
start_here:
|
|
/* ptr to current */
|
|
lis r2,init_task@h
|
|
ori r2,r2,init_task@l
|
|
/* Set up for using our exception vectors */
|
|
/* ptr to phys current thread */
|
|
tophys(r4,r2)
|
|
addi r4,r4,THREAD /* init task's THREAD */
|
|
mtspr SPRN_SPRG_THREAD,r4
|
|
BEGIN_MMU_FTR_SECTION
|
|
lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
|
|
ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
|
|
rlwinm r4, r4, 4, 0xffff01ff
|
|
mtspr SPRN_SDR1, r4
|
|
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_HPTE_TABLE)
|
|
|
|
/* stack */
|
|
lis r1,init_thread_union@ha
|
|
addi r1,r1,init_thread_union@l
|
|
li r0,0
|
|
stwu r0,THREAD_SIZE-STACK_FRAME_MIN_SIZE(r1)
|
|
/*
|
|
* Do early platform-specific initialization,
|
|
* and set up the MMU.
|
|
*/
|
|
#ifdef CONFIG_KASAN
|
|
bl kasan_early_init
|
|
#endif
|
|
li r3,0
|
|
mr r4,r31
|
|
bl machine_init
|
|
bl __save_cpu_setup
|
|
bl MMU_init
|
|
bl MMU_init_hw_patch
|
|
|
|
/*
|
|
* Go back to running unmapped so we can load up new values
|
|
* for SDR1 (hash table pointer) and the segment registers
|
|
* and change to using our exception vectors.
|
|
*/
|
|
lis r4,2f@h
|
|
ori r4,r4,2f@l
|
|
tophys(r4,r4)
|
|
li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
|
|
|
|
.align 4
|
|
mtspr SPRN_SRR0,r4
|
|
mtspr SPRN_SRR1,r3
|
|
rfi
|
|
/* Load up the kernel context */
|
|
2: bl load_up_mmu
|
|
|
|
#ifdef CONFIG_BDI_SWITCH
|
|
/* Add helper information for the Abatron bdiGDB debugger.
|
|
* We do this here because we know the mmu is disabled, and
|
|
* will be enabled for real in just a few instructions.
|
|
*/
|
|
lis r5, abatron_pteptrs@h
|
|
ori r5, r5, abatron_pteptrs@l
|
|
stw r5, 0xf0(0) /* This much match your Abatron config */
|
|
lis r6, swapper_pg_dir@h
|
|
ori r6, r6, swapper_pg_dir@l
|
|
tophys(r5, r5)
|
|
stw r6, 0(r5)
|
|
#endif /* CONFIG_BDI_SWITCH */
|
|
|
|
/* Now turn on the MMU for real! */
|
|
li r4,MSR_KERNEL
|
|
lis r3,start_kernel@h
|
|
ori r3,r3,start_kernel@l
|
|
mtspr SPRN_SRR0,r3
|
|
mtspr SPRN_SRR1,r4
|
|
rfi
|
|
|
|
/*
|
|
* An undocumented "feature" of 604e requires that the v bit
|
|
* be cleared before changing BAT values.
|
|
*
|
|
* Also, newer IBM firmware does not clear bat3 and 4 so
|
|
* this makes sure it's done.
|
|
* -- Cort
|
|
*/
|
|
SYM_FUNC_START_LOCAL(clear_bats)
|
|
li r10,0
|
|
|
|
mtspr SPRN_DBAT0U,r10
|
|
mtspr SPRN_DBAT0L,r10
|
|
mtspr SPRN_DBAT1U,r10
|
|
mtspr SPRN_DBAT1L,r10
|
|
mtspr SPRN_DBAT2U,r10
|
|
mtspr SPRN_DBAT2L,r10
|
|
mtspr SPRN_DBAT3U,r10
|
|
mtspr SPRN_DBAT3L,r10
|
|
mtspr SPRN_IBAT0U,r10
|
|
mtspr SPRN_IBAT0L,r10
|
|
mtspr SPRN_IBAT1U,r10
|
|
mtspr SPRN_IBAT1L,r10
|
|
mtspr SPRN_IBAT2U,r10
|
|
mtspr SPRN_IBAT2L,r10
|
|
mtspr SPRN_IBAT3U,r10
|
|
mtspr SPRN_IBAT3L,r10
|
|
BEGIN_MMU_FTR_SECTION
|
|
/* Here's a tweak: at this point, CPU setup have
|
|
* not been called yet, so HIGH_BAT_EN may not be
|
|
* set in HID0 for the 745x processors. However, it
|
|
* seems that doesn't affect our ability to actually
|
|
* write to these SPRs.
|
|
*/
|
|
mtspr SPRN_DBAT4U,r10
|
|
mtspr SPRN_DBAT4L,r10
|
|
mtspr SPRN_DBAT5U,r10
|
|
mtspr SPRN_DBAT5L,r10
|
|
mtspr SPRN_DBAT6U,r10
|
|
mtspr SPRN_DBAT6L,r10
|
|
mtspr SPRN_DBAT7U,r10
|
|
mtspr SPRN_DBAT7L,r10
|
|
mtspr SPRN_IBAT4U,r10
|
|
mtspr SPRN_IBAT4L,r10
|
|
mtspr SPRN_IBAT5U,r10
|
|
mtspr SPRN_IBAT5L,r10
|
|
mtspr SPRN_IBAT6U,r10
|
|
mtspr SPRN_IBAT6L,r10
|
|
mtspr SPRN_IBAT7U,r10
|
|
mtspr SPRN_IBAT7L,r10
|
|
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
|
|
blr
|
|
SYM_FUNC_END(clear_bats)
|
|
|
|
_GLOBAL(update_bats)
|
|
lis r4, 1f@h
|
|
ori r4, r4, 1f@l
|
|
tophys(r4, r4)
|
|
mfmsr r6
|
|
mflr r7
|
|
li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR)
|
|
rlwinm r0, r6, 0, ~MSR_RI
|
|
rlwinm r0, r0, 0, ~MSR_EE
|
|
mtmsr r0
|
|
|
|
.align 4
|
|
mtspr SPRN_SRR0, r4
|
|
mtspr SPRN_SRR1, r3
|
|
rfi
|
|
1: bl clear_bats
|
|
lis r3, BATS@ha
|
|
addi r3, r3, BATS@l
|
|
tophys(r3, r3)
|
|
LOAD_BAT(0, r3, r4, r5)
|
|
LOAD_BAT(1, r3, r4, r5)
|
|
LOAD_BAT(2, r3, r4, r5)
|
|
LOAD_BAT(3, r3, r4, r5)
|
|
BEGIN_MMU_FTR_SECTION
|
|
LOAD_BAT(4, r3, r4, r5)
|
|
LOAD_BAT(5, r3, r4, r5)
|
|
LOAD_BAT(6, r3, r4, r5)
|
|
LOAD_BAT(7, r3, r4, r5)
|
|
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
|
|
li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI)
|
|
mtmsr r3
|
|
mtspr SPRN_SRR0, r7
|
|
mtspr SPRN_SRR1, r6
|
|
rfi
|
|
|
|
SYM_FUNC_START_LOCAL(flush_tlbs)
|
|
lis r10, 0x40
|
|
1: addic. r10, r10, -0x1000
|
|
tlbie r10
|
|
bgt 1b
|
|
sync
|
|
blr
|
|
SYM_FUNC_END(flush_tlbs)
|
|
|
|
SYM_FUNC_START_LOCAL(mmu_off)
|
|
addi r4, r3, __after_mmu_off - _start
|
|
mfmsr r3
|
|
andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
|
|
beqlr
|
|
andc r3,r3,r0
|
|
|
|
.align 4
|
|
mtspr SPRN_SRR0,r4
|
|
mtspr SPRN_SRR1,r3
|
|
sync
|
|
rfi
|
|
SYM_FUNC_END(mmu_off)
|
|
|
|
/* We use one BAT to map up to 256M of RAM at _PAGE_OFFSET */
|
|
SYM_FUNC_START_LOCAL(initial_bats)
|
|
lis r11,PAGE_OFFSET@h
|
|
tophys(r8,r11)
|
|
#ifdef CONFIG_SMP
|
|
ori r8,r8,0x12 /* R/W access, M=1 */
|
|
#else
|
|
ori r8,r8,2 /* R/W access */
|
|
#endif /* CONFIG_SMP */
|
|
ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
|
|
|
|
mtspr SPRN_DBAT0L,r8 /* N.B. 6xx have valid */
|
|
mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
|
|
mtspr SPRN_IBAT0L,r8
|
|
mtspr SPRN_IBAT0U,r11
|
|
isync
|
|
blr
|
|
SYM_FUNC_END(initial_bats)
|
|
|
|
#ifdef CONFIG_BOOTX_TEXT
|
|
SYM_FUNC_START_LOCAL(setup_disp_bat)
|
|
/*
|
|
* setup the display bat prepared for us in prom.c
|
|
*/
|
|
mflr r8
|
|
bl reloc_offset
|
|
mtlr r8
|
|
addis r8,r3,disp_BAT@ha
|
|
addi r8,r8,disp_BAT@l
|
|
cmpwi cr0,r8,0
|
|
beqlr
|
|
lwz r11,0(r8)
|
|
lwz r8,4(r8)
|
|
mtspr SPRN_DBAT3L,r8
|
|
mtspr SPRN_DBAT3U,r11
|
|
blr
|
|
SYM_FUNC_END(setup_disp_bat)
|
|
#endif /* CONFIG_BOOTX_TEXT */
|
|
|
|
#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
|
|
SYM_FUNC_START_LOCAL(setup_cpm_bat)
|
|
lis r8, 0xf000
|
|
ori r8, r8, 0x002a
|
|
mtspr SPRN_DBAT1L, r8
|
|
|
|
lis r11, 0xf000
|
|
ori r11, r11, (BL_1M << 2) | 2
|
|
mtspr SPRN_DBAT1U, r11
|
|
|
|
blr
|
|
SYM_FUNC_END(setup_cpm_bat)
|
|
#endif
|
|
|
|
#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
|
|
SYM_FUNC_START_LOCAL(setup_usbgecko_bat)
|
|
/* prepare a BAT for early io */
|
|
#if defined(CONFIG_GAMECUBE)
|
|
lis r8, 0x0c00
|
|
#elif defined(CONFIG_WII)
|
|
lis r8, 0x0d00
|
|
#else
|
|
#error Invalid platform for USB Gecko based early debugging.
|
|
#endif
|
|
/*
|
|
* The virtual address used must match the virtual address
|
|
* associated to the fixmap entry FIX_EARLY_DEBUG_BASE.
|
|
*/
|
|
lis r11, 0xfffe /* top 128K */
|
|
ori r8, r8, 0x002a /* uncached, guarded ,rw */
|
|
ori r11, r11, 0x2 /* 128K, Vs=1, Vp=0 */
|
|
mtspr SPRN_DBAT1L, r8
|
|
mtspr SPRN_DBAT1U, r11
|
|
blr
|
|
SYM_FUNC_END(setup_usbgecko_bat)
|
|
#endif
|
|
|
|
.data
|