f4a81f5a85
Just like for INVALL, GICv4.1 has grown a VPE-aware INVLPI register. Let's plumb it in and make use of the DirectLPI code in that case. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Link: https://lore.kernel.org/r/20191224111055.11836-16-maz@kernel.org |
||
---|---|---|
.. | ||
arm-gic-common.h | ||
arm-gic-v3.h | ||
arm-gic-v4.h | ||
arm-gic.h | ||
arm-vic.h | ||
chained_irq.h | ||
irq-bcm2836.h | ||
irq-davinci-aintc.h | ||
irq-davinci-cp-intc.h | ||
irq-ixp4xx.h | ||
irq-madera.h | ||
irq-omap-intc.h | ||
irq-partition-percpu.h | ||
irq-sa11x0.h | ||
mmp.h | ||
mxs.h | ||
versatile-fpga.h | ||
xtensa-mx.h | ||
xtensa-pic.h |