184 lines
4.6 KiB
C
184 lines
4.6 KiB
C
/*
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* OMAP4 SMP source file. It contains platform specific fucntions
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* needed for the linux smp kernel.
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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*
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Platform file needed for the OMAP4 SMP. This file is based on arm
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* realview smp platform.
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* * Copyright (c) 2002 ARM Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/gic.h>
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#include <asm/smp_scu.h>
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#include <mach/hardware.h>
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#include <mach/omap-secure.h>
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#include "iomap.h"
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#include "common.h"
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#include "clockdomain.h"
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/* SCU base address */
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static void __iomem *scu_base;
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static DEFINE_SPINLOCK(boot_lock);
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void __iomem *omap4_get_scu_base(void)
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{
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return scu_base;
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}
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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/*
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* Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
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* OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
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* init and for CPU1, a secure PPA API provided. CPU0 must be ON
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* while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
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* OMAP443X GP devices- SMP bit isn't accessible.
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* OMAP446X GP devices - SMP bit access is enabled on both CPUs.
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*/
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if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
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omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
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4, 0, 0, 0, 0, 0);
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/*
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* If any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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static struct clockdomain *cpu1_clkdm;
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static bool booted;
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* Update the AuxCoreBoot0 with boot state for secondary core.
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* omap_secondary_startup() routine will hold the secondary core till
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* the AuxCoreBoot1 register is updated with cpu state
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* A barrier is added to ensure that write buffer is drained
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*/
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omap_modify_auxcoreboot0(0x200, 0xfffffdff);
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flush_cache_all();
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smp_wmb();
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if (!cpu1_clkdm)
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cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
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/*
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* The SGI(Software Generated Interrupts) are not wakeup capable
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* from low power states. This is known limitation on OMAP4 and
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* needs to be worked around by using software forced clockdomain
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* wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
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* software force wakeup. The clockdomain is then put back to
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* hardware supervised mode.
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* More details can be found in OMAP4430 TRM - Version J
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* Section :
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* 4.3.4.2 Power States of CPU0 and CPU1
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*/
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if (booted) {
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clkdm_wakeup(cpu1_clkdm);
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clkdm_allow_idle(cpu1_clkdm);
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} else {
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dsb_sev();
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booted = true;
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}
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gic_raise_softirq(cpumask_of(cpu), 1);
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/*
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* Now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return 0;
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}
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static void __init wakeup_secondary(void)
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{
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/*
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* Write the address of secondary startup routine into the
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* AuxCoreBoot1 where ROM code will jump and start executing
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* on secondary core once out of WFE
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* A barrier is added to ensure that write buffer is drained
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*/
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omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
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smp_wmb();
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/*
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* Send a 'sev' to wake the secondary core from WFE.
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* Drain the outstanding writes to memory
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*/
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dsb_sev();
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mb();
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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void __init smp_init_cpus(void)
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{
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unsigned int i, ncores;
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/*
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* Currently we can't call ioremap here because
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* SoC detection won't work until after init_early.
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*/
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scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
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BUG_ON(!scu_base);
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ncores = scu_get_core_count(scu_base);
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/* sanity check */
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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{
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/*
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* Initialise the SCU and wake up the secondary core using
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* wakeup_secondary().
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*/
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scu_enable(scu_base);
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wakeup_secondary();
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}
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