416 lines
8.7 KiB
Plaintext
416 lines
8.7 KiB
Plaintext
/dts-v1/;
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-apq8084.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Qualcomm APQ 8084";
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compatible = "qcom,apq8084";
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interrupt-parent = <&intc>;
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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smem_mem: smem_region@fa00000 {
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reg = <0xfa00000 0x200000>;
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no-map;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "qcom,krait";
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reg = <0>;
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "qcom,krait";
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reg = <1>;
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "qcom,krait";
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reg = <2>;
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc2>;
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qcom,saw = <&saw2>;
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "qcom,krait";
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reg = <3>;
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc3>;
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qcom,saw = <&saw3>;
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cpu-idle-states = <&CPU_SPC>;
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};
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L2: l2-cache {
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compatible = "qcom,arch-cache";
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cache-level = <2>;
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qcom,saw = <&saw_l2>;
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};
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idle-states {
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CPU_SPC: spc {
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compatible = "qcom,idle-state-spc",
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"arm,idle-state";
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entry-latency-us = <150>;
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exit-latency-us = <200>;
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min-residency-us = <2000>;
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};
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm";
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clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
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clock-names = "core", "bus", "iface";
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};
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};
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cpu-pmu {
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compatible = "qcom,krait-pmu";
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interrupts = <1 7 0xf04>;
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};
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clocks {
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xo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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};
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sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 2 0xf08>,
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<1 3 0xf08>,
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<1 4 0xf08>,
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<1 1 0xf08>;
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clock-frequency = <19200000>;
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};
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smem {
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compatible = "qcom,smem";
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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intc: interrupt-controller@f9000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0xf9000000 0x1000>,
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<0xf9002000 0x1000>;
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};
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apcs: syscon@f9011000 {
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compatible = "syscon";
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reg = <0xf9011000 0x1000>;
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};
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timer@f9020000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xf9020000 0x1000>;
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clock-frequency = <19200000>;
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frame@f9021000 {
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frame-number = <0>;
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interrupts = <0 8 0x4>,
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<0 7 0x4>;
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reg = <0xf9021000 0x1000>,
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<0xf9022000 0x1000>;
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};
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frame@f9023000 {
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frame-number = <1>;
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interrupts = <0 9 0x4>;
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reg = <0xf9023000 0x1000>;
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status = "disabled";
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};
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frame@f9024000 {
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frame-number = <2>;
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interrupts = <0 10 0x4>;
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reg = <0xf9024000 0x1000>;
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status = "disabled";
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};
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frame@f9025000 {
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frame-number = <3>;
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interrupts = <0 11 0x4>;
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reg = <0xf9025000 0x1000>;
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status = "disabled";
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};
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frame@f9026000 {
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frame-number = <4>;
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interrupts = <0 12 0x4>;
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reg = <0xf9026000 0x1000>;
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status = "disabled";
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};
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frame@f9027000 {
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frame-number = <5>;
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interrupts = <0 13 0x4>;
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reg = <0xf9027000 0x1000>;
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status = "disabled";
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};
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frame@f9028000 {
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frame-number = <6>;
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interrupts = <0 14 0x4>;
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reg = <0xf9028000 0x1000>;
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status = "disabled";
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};
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};
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saw0: power-controller@f9089000 {
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compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
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reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
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};
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saw1: power-controller@f9099000 {
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compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
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reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
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};
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saw2: power-controller@f90a9000 {
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compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
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reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
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};
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saw3: power-controller@f90b9000 {
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compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
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reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
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};
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saw_l2: power-controller@f9012000 {
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compatible = "qcom,saw2";
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reg = <0xf9012000 0x1000>;
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regulator;
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};
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acc0: clock-controller@f9088000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf9088000 0x1000>,
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<0xf9008000 0x1000>;
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};
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acc1: clock-controller@f9098000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf9098000 0x1000>,
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<0xf9008000 0x1000>;
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};
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acc2: clock-controller@f90a8000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf90a8000 0x1000>,
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<0xf9008000 0x1000>;
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};
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acc3: clock-controller@f90b8000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf90b8000 0x1000>,
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<0xf9008000 0x1000>;
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};
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restart@fc4ab000 {
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compatible = "qcom,pshold";
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reg = <0xfc4ab000 0x4>;
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};
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gcc: clock-controller@fc400000 {
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compatible = "qcom,gcc-apq8084";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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reg = <0xfc400000 0x4000>;
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};
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tcsr_mutex_regs: syscon@fd484000 {
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compatible = "syscon";
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reg = <0xfd484000 0x2000>;
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_regs 0 0x80>;
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#hwlock-cells = <1>;
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};
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rpm_msg_ram: memory@fc428000 {
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compatible = "qcom,rpm-msg-ram";
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reg = <0xfc428000 0x4000>;
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};
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tlmm: pinctrl@fd510000 {
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compatible = "qcom,apq8084-pinctrl";
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reg = <0xfd510000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 208 0>;
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};
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blsp2_uart2: serial@f995e000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf995e000 0x1000>;
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interrupts = <0 114 0x0>;
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clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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sdhci@f9824900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <0 123 0>, <0 138 0>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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sdhci@f98a4900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <0 125 0>, <0 221 0>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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spmi_bus: spmi@fc4cf000 {
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compatible = "qcom,spmi-pmic-arb";
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reg-names = "core", "intr", "cnfg";
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reg = <0xfc4cf000 0x1000>,
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<0xfc4cb000 0x1000>,
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<0xfc4ca000 0x1000>;
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interrupt-names = "periph_irq";
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interrupts = <0 190 0>;
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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};
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};
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smd {
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compatible = "qcom,smd";
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rpm {
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interrupts = <0 168 1>;
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qcom,ipc = <&apcs 8 0>;
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qcom,smd-edge = <15>;
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rpm_requests {
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compatible = "qcom,rpm-apq8084";
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qcom,smd-channels = "rpm_requests";
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pma8084-regulators {
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compatible = "qcom,rpm-pma8084-regulators";
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pma8084_s1: s1 {};
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pma8084_s2: s2 {};
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pma8084_s3: s3 {};
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pma8084_s4: s4 {};
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pma8084_s5: s5 {};
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pma8084_s6: s6 {};
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pma8084_s7: s7 {};
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pma8084_s8: s8 {};
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pma8084_s9: s9 {};
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pma8084_s10: s10 {};
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pma8084_s11: s11 {};
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pma8084_s12: s12 {};
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pma8084_l1: l1 {};
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pma8084_l2: l2 {};
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pma8084_l3: l3 {};
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pma8084_l4: l4 {};
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pma8084_l5: l5 {};
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pma8084_l6: l6 {};
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pma8084_l7: l7 {};
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pma8084_l8: l8 {};
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pma8084_l9: l9 {};
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pma8084_l10: l10 {};
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pma8084_l11: l11 {};
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pma8084_l12: l12 {};
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pma8084_l13: l13 {};
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pma8084_l14: l14 {};
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pma8084_l15: l15 {};
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pma8084_l16: l16 {};
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pma8084_l17: l17 {};
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pma8084_l18: l18 {};
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pma8084_l19: l19 {};
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pma8084_l20: l20 {};
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pma8084_l21: l21 {};
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pma8084_l22: l22 {};
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pma8084_l23: l23 {};
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pma8084_l24: l24 {};
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pma8084_l25: l25 {};
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pma8084_l26: l26 {};
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pma8084_l27: l27 {};
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pma8084_lvs1: lvs1 {};
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pma8084_lvs2: lvs2 {};
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pma8084_lvs3: lvs3 {};
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pma8084_lvs4: lvs4 {};
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pma8084_5vs1: 5vs1 {};
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};
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};
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};
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};
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};
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