602 lines
15 KiB
C
602 lines
15 KiB
C
/*
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* Ralink RT3662/RT3883 SoC PCI support
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*
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* Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/platform_device.h>
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#include <asm/mach-ralink/rt3883.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#define RT3883_MEMORY_BASE 0x00000000
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#define RT3883_MEMORY_SIZE 0x02000000
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#define RT3883_PCI_REG_PCICFG 0x00
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#define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
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#define RT3883_PCICFG_P2P_BR_DEVNUM_S 16
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#define RT3883_PCICFG_PCIRST BIT(1)
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#define RT3883_PCI_REG_PCIRAW 0x04
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#define RT3883_PCI_REG_PCIINT 0x08
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#define RT3883_PCI_REG_PCIENA 0x0c
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#define RT3883_PCI_REG_CFGADDR 0x20
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#define RT3883_PCI_REG_CFGDATA 0x24
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#define RT3883_PCI_REG_MEMBASE 0x28
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#define RT3883_PCI_REG_IOBASE 0x2c
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#define RT3883_PCI_REG_ARBCTL 0x80
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#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
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#define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
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#define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
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#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
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#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
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#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
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#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
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#define RT3883_PCI_MODE_NONE 0
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#define RT3883_PCI_MODE_PCI BIT(0)
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#define RT3883_PCI_MODE_PCIE BIT(1)
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#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
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#define RT3883_PCI_IRQ_COUNT 32
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#define RT3883_P2P_BR_DEVNUM 1
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struct rt3883_pci_controller {
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void __iomem *base;
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struct device_node *intc_of_node;
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struct irq_domain *irq_domain;
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struct pci_controller pci_controller;
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struct resource io_res;
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struct resource mem_res;
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bool pcie_ready;
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};
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static inline struct rt3883_pci_controller *
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pci_bus_to_rt3883_controller(struct pci_bus *bus)
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{
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struct pci_controller *hose;
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hose = (struct pci_controller *) bus->sysdata;
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return container_of(hose, struct rt3883_pci_controller, pci_controller);
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}
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static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
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unsigned reg)
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{
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return ioread32(rpc->base + reg);
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}
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static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
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u32 val, unsigned reg)
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{
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iowrite32(val, rpc->base + reg);
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}
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static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
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unsigned int func, unsigned int where)
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{
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return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
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0x80000000;
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}
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static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
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unsigned bus, unsigned slot,
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unsigned func, unsigned reg)
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{
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unsigned long flags;
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u32 address;
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u32 ret;
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address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
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rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
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ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
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return ret;
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}
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static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
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unsigned bus, unsigned slot,
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unsigned func, unsigned reg, u32 val)
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{
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unsigned long flags;
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u32 address;
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address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
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rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
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rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
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}
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static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct rt3883_pci_controller *rpc;
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u32 pending;
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rpc = irq_get_handler_data(irq);
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pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
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rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
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if (!pending) {
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spurious_interrupt();
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return;
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}
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while (pending) {
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unsigned bit = __ffs(pending);
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irq = irq_find_mapping(rpc->irq_domain, bit);
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generic_handle_irq(irq);
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pending &= ~BIT(bit);
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}
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}
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static void rt3883_pci_irq_unmask(struct irq_data *d)
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{
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struct rt3883_pci_controller *rpc;
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u32 t;
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rpc = irq_data_get_irq_chip_data(d);
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t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
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rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
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/* flush write */
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rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
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}
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static void rt3883_pci_irq_mask(struct irq_data *d)
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{
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struct rt3883_pci_controller *rpc;
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u32 t;
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rpc = irq_data_get_irq_chip_data(d);
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t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
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rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
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/* flush write */
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rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
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}
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static struct irq_chip rt3883_pci_irq_chip = {
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.name = "RT3883 PCI",
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.irq_mask = rt3883_pci_irq_mask,
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.irq_unmask = rt3883_pci_irq_unmask,
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.irq_mask_ack = rt3883_pci_irq_mask,
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};
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static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, d->host_data);
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return 0;
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}
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static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
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.map = rt3883_pci_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static int rt3883_pci_irq_init(struct device *dev,
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struct rt3883_pci_controller *rpc)
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{
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int irq;
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irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
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if (irq == 0) {
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dev_err(dev, "%s has no IRQ",
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of_node_full_name(rpc->intc_of_node));
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return -EINVAL;
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}
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/* disable all interrupts */
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rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
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rpc->irq_domain =
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irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
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&rt3883_pci_irq_domain_ops,
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rpc);
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if (!rpc->irq_domain) {
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dev_err(dev, "unable to add IRQ domain\n");
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return -ENODEV;
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}
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irq_set_handler_data(irq, rpc);
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irq_set_chained_handler(irq, rt3883_pci_irq_handler);
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return 0;
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}
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static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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struct rt3883_pci_controller *rpc;
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unsigned long flags;
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u32 address;
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u32 data;
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rpc = pci_bus_to_rt3883_controller(bus);
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if (!rpc->pcie_ready && bus->number == 1)
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return PCIBIOS_DEVICE_NOT_FOUND;
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address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), where);
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rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
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data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
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switch (size) {
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case 1:
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*val = (data >> ((where & 3) << 3)) & 0xff;
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break;
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case 2:
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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break;
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case 4:
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*val = data;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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struct rt3883_pci_controller *rpc;
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unsigned long flags;
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u32 address;
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u32 data;
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rpc = pci_bus_to_rt3883_controller(bus);
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if (!rpc->pcie_ready && bus->number == 1)
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return PCIBIOS_DEVICE_NOT_FOUND;
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address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), where);
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rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
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data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
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switch (size) {
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case 1:
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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break;
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case 2:
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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break;
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case 4:
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data = val;
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break;
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}
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rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops rt3883_pci_ops = {
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.read = rt3883_pci_config_read,
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.write = rt3883_pci_config_write,
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};
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static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
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{
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u32 syscfg1;
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u32 rstctrl;
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u32 clkcfg1;
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u32 t;
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rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
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syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
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clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
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if (mode & RT3883_PCI_MODE_PCIE) {
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rstctrl |= RT3883_RSTCTRL_PCIE;
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rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
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/* setup PCI PAD drive mode */
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syscfg1 &= ~(0x30);
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syscfg1 |= (2 << 4);
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rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
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t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
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t &= ~BIT(31);
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rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
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t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
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t &= 0x80ffffff;
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rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
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t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
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t |= 0xa << 24;
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rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
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t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
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t |= BIT(31);
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rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
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msleep(50);
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rstctrl &= ~RT3883_RSTCTRL_PCIE;
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rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
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}
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syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
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clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
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if (mode & RT3883_PCI_MODE_PCI) {
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clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
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rstctrl &= ~RT3883_RSTCTRL_PCI;
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}
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if (mode & RT3883_PCI_MODE_PCIE) {
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clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
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rstctrl &= ~RT3883_RSTCTRL_PCIE;
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}
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rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
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rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
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rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
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msleep(500);
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/*
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* setup the device number of the P2P bridge
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* and de-assert the reset line
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*/
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t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
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rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
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/* flush write */
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rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
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msleep(500);
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if (mode & RT3883_PCI_MODE_PCIE) {
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msleep(500);
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t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
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rpc->pcie_ready = t & BIT(0);
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if (!rpc->pcie_ready) {
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/* reset the PCIe block */
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t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
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t |= RT3883_RSTCTRL_PCIE;
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rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
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t &= ~RT3883_RSTCTRL_PCIE;
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rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
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/* turn off PCIe clock */
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t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
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t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
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rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
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t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
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t &= ~0xf000c080;
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rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
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}
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}
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/* enable PCI arbiter */
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rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
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}
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static int rt3883_pci_probe(struct platform_device *pdev)
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{
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struct rt3883_pci_controller *rpc;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct resource *res;
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struct device_node *child;
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u32 val;
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int err;
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int mode;
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rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
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if (!rpc)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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rpc->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(rpc->base))
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return PTR_ERR(rpc->base);
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/* find the interrupt controller child node */
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for_each_child_of_node(np, child) {
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if (of_get_property(child, "interrupt-controller", NULL) &&
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of_node_get(child)) {
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rpc->intc_of_node = child;
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break;
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}
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}
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if (!rpc->intc_of_node) {
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dev_err(dev, "%s has no %s child node",
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of_node_full_name(rpc->intc_of_node),
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"interrupt controller");
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return -EINVAL;
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}
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/* find the PCI host bridge child node */
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for_each_child_of_node(np, child) {
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if (child->type &&
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of_node_cmp(child->type, "pci") == 0 &&
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of_node_get(child)) {
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rpc->pci_controller.of_node = child;
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break;
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}
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}
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if (!rpc->pci_controller.of_node) {
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dev_err(dev, "%s has no %s child node",
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of_node_full_name(rpc->intc_of_node),
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"PCI host bridge");
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err = -EINVAL;
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goto err_put_intc_node;
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}
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mode = RT3883_PCI_MODE_NONE;
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for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
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int devfn;
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if (!child->type ||
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of_node_cmp(child->type, "pci") != 0)
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continue;
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devfn = of_pci_get_devfn(child);
|
|
if (devfn < 0)
|
|
continue;
|
|
|
|
switch (PCI_SLOT(devfn)) {
|
|
case 1:
|
|
mode |= RT3883_PCI_MODE_PCIE;
|
|
break;
|
|
|
|
case 17:
|
|
case 18:
|
|
mode |= RT3883_PCI_MODE_PCI;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (mode == RT3883_PCI_MODE_NONE) {
|
|
dev_err(dev, "unable to determine PCI mode\n");
|
|
err = -EINVAL;
|
|
goto err_put_hb_node;
|
|
}
|
|
|
|
dev_info(dev, "mode:%s%s\n",
|
|
(mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
|
|
(mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
|
|
|
|
rt3883_pci_preinit(rpc, mode);
|
|
|
|
rpc->pci_controller.pci_ops = &rt3883_pci_ops;
|
|
rpc->pci_controller.io_resource = &rpc->io_res;
|
|
rpc->pci_controller.mem_resource = &rpc->mem_res;
|
|
|
|
/* Load PCI I/O and memory resources from DT */
|
|
pci_load_of_ranges(&rpc->pci_controller,
|
|
rpc->pci_controller.of_node);
|
|
|
|
rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
|
|
rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
|
|
|
|
ioport_resource.start = rpc->io_res.start;
|
|
ioport_resource.end = rpc->io_res.end;
|
|
|
|
/* PCI */
|
|
rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
|
|
rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
|
|
rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
|
|
rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
|
|
rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
|
|
|
|
/* PCIe */
|
|
rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
|
|
rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
|
|
rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
|
|
rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
|
|
rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
|
|
|
|
err = rt3883_pci_irq_init(dev, rpc);
|
|
if (err)
|
|
goto err_put_hb_node;
|
|
|
|
/* PCIe */
|
|
val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
|
|
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
|
rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
|
|
|
|
/* PCI */
|
|
val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
|
|
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
|
rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
|
|
|
|
if (mode == RT3883_PCI_MODE_PCIE) {
|
|
rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
|
|
rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
|
|
|
|
rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
|
|
PCI_BASE_ADDRESS_0,
|
|
RT3883_MEMORY_BASE);
|
|
/* flush write */
|
|
rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
|
|
PCI_BASE_ADDRESS_0);
|
|
} else {
|
|
rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
|
|
PCI_IO_BASE, 0x00000101);
|
|
}
|
|
|
|
register_pci_controller(&rpc->pci_controller);
|
|
|
|
return 0;
|
|
|
|
err_put_hb_node:
|
|
of_node_put(rpc->pci_controller.of_node);
|
|
err_put_intc_node:
|
|
of_node_put(rpc->intc_of_node);
|
|
return err;
|
|
}
|
|
|
|
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
|
{
|
|
return of_irq_parse_and_map_pci(dev, slot, pin);
|
|
}
|
|
|
|
int pcibios_plat_dev_init(struct pci_dev *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id rt3883_pci_ids[] = {
|
|
{ .compatible = "ralink,rt3883-pci" },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, rt3883_pci_ids);
|
|
|
|
static struct platform_driver rt3883_pci_driver = {
|
|
.probe = rt3883_pci_probe,
|
|
.driver = {
|
|
.name = "rt3883-pci",
|
|
.of_match_table = of_match_ptr(rt3883_pci_ids),
|
|
},
|
|
};
|
|
|
|
static int __init rt3883_pci_init(void)
|
|
{
|
|
return platform_driver_register(&rt3883_pci_driver);
|
|
}
|
|
|
|
postcore_initcall(rt3883_pci_init);
|