72 lines
1.5 KiB
C
72 lines
1.5 KiB
C
/*
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* x86 TSC related functions
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*/
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#ifndef _ASM_X86_TSC_H
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#define _ASM_X86_TSC_H
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#include <asm/processor.h>
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#define NS_SCALE 10 /* 2^10, carefully chosen */
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#define US_SCALE 32 /* 2^32, arbitralrily chosen */
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/*
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* Standard way to access the cycle counter.
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*/
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typedef unsigned long long cycles_t;
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extern unsigned int cpu_khz;
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extern unsigned int tsc_khz;
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extern void disable_TSC(void);
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static inline cycles_t get_cycles(void)
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{
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unsigned long long ret = 0;
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#ifndef CONFIG_X86_TSC
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if (!cpu_has_tsc)
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return 0;
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#endif
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rdtscll(ret);
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return ret;
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}
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static __always_inline cycles_t vget_cycles(void)
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{
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/*
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* We only do VDSOs on TSC capable CPUs, so this shouldn't
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* access boot_cpu_data (which is not VDSO-safe):
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*/
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#ifndef CONFIG_X86_TSC
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if (!cpu_has_tsc)
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return 0;
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#endif
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return (cycles_t)__native_read_tsc();
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}
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extern void tsc_init(void);
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extern void mark_tsc_unstable(char *reason);
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extern int unsynchronized_tsc(void);
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extern int check_tsc_unstable(void);
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extern int check_tsc_disabled(void);
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extern unsigned long native_calibrate_tsc(void);
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extern int tsc_clocksource_reliable;
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/*
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* Boot-time check whether the TSCs are synchronized across
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* all CPUs/cores:
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*/
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extern void check_tsc_sync_source(int cpu);
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extern void check_tsc_sync_target(void);
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extern int notsc_setup(char *);
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extern void tsc_save_sched_clock_state(void);
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extern void tsc_restore_sched_clock_state(void);
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/* MSR based TSC calibration for Intel Atom SoC platforms */
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unsigned long try_msr_calibrate_tsc(void);
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#endif /* _ASM_X86_TSC_H */
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