599 lines
12 KiB
C
599 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm/include/asm/assembler.h
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*
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* Copyright (C) 1996-2000 Russell King
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*
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* This file contains arm architecture specific defines
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* for the different processors.
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*
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* Do not include any C declarations in this file - it is included by
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* assembler source.
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*/
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#ifndef __ASM_ASSEMBLER_H__
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#define __ASM_ASSEMBLER_H__
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#ifndef __ASSEMBLY__
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#error "Only include this from assembly code"
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#endif
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#include <asm/ptrace.h>
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#include <asm/opcodes-virt.h>
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#include <asm/asm-offsets.h>
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#include <asm/page.h>
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#include <asm/thread_info.h>
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#include <asm/uaccess-asm.h>
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#define IOMEM(x) (x)
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/*
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* Endian independent macros for shifting bytes within registers.
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*/
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#ifndef __ARMEB__
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#define lspull lsr
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#define lspush lsl
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#define get_byte_0 lsl #0
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#define get_byte_1 lsr #8
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#define get_byte_2 lsr #16
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#define get_byte_3 lsr #24
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#define put_byte_0 lsl #0
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#define put_byte_1 lsl #8
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#define put_byte_2 lsl #16
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#define put_byte_3 lsl #24
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#else
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#define lspull lsl
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#define lspush lsr
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#define get_byte_0 lsr #24
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#define get_byte_1 lsr #16
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#define get_byte_2 lsr #8
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#define get_byte_3 lsl #0
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#define put_byte_0 lsl #24
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#define put_byte_1 lsl #16
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#define put_byte_2 lsl #8
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#define put_byte_3 lsl #0
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#endif
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/* Select code for any configuration running in BE8 mode */
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#ifdef CONFIG_CPU_ENDIAN_BE8
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#define ARM_BE8(code...) code
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#else
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#define ARM_BE8(code...)
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#endif
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/*
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* Data preload for architectures that support it
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*/
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#if __LINUX_ARM_ARCH__ >= 5
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#define PLD(code...) code
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#else
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#define PLD(code...)
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#endif
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/*
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* This can be used to enable code to cacheline align the destination
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* pointer when bulk writing to memory. Experiments on StrongARM and
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* XScale didn't show this a worthwhile thing to do when the cache is not
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* set to write-allocate (this would need further testing on XScale when WA
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* is used).
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*
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* On Feroceon there is much to gain however, regardless of cache mode.
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*/
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#ifdef CONFIG_CPU_FEROCEON
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#define CALGN(code...) code
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#else
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#define CALGN(code...)
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#endif
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#define IMM12_MASK 0xfff
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/*
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* Enable and disable interrupts
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*/
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#if __LINUX_ARM_ARCH__ >= 6
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.macro disable_irq_notrace
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cpsid i
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.endm
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.macro enable_irq_notrace
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cpsie i
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.endm
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#else
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.macro disable_irq_notrace
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msr cpsr_c, #PSR_I_BIT | SVC_MODE
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.endm
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.macro enable_irq_notrace
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msr cpsr_c, #SVC_MODE
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.endm
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#endif
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.macro asm_trace_hardirqs_off, save=1
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#if defined(CONFIG_TRACE_IRQFLAGS)
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.if \save
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stmdb sp!, {r0-r3, ip, lr}
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.endif
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bl trace_hardirqs_off
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.if \save
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ldmia sp!, {r0-r3, ip, lr}
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.endif
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#endif
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.endm
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.macro asm_trace_hardirqs_on, cond=al, save=1
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#if defined(CONFIG_TRACE_IRQFLAGS)
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/*
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* actually the registers should be pushed and pop'd conditionally, but
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* after bl the flags are certainly clobbered
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*/
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.if \save
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stmdb sp!, {r0-r3, ip, lr}
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.endif
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bl\cond trace_hardirqs_on
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.if \save
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ldmia sp!, {r0-r3, ip, lr}
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.endif
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#endif
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.endm
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.macro disable_irq, save=1
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disable_irq_notrace
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asm_trace_hardirqs_off \save
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.endm
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.macro enable_irq
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asm_trace_hardirqs_on
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enable_irq_notrace
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.endm
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/*
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* Save the current IRQ state and disable IRQs. Note that this macro
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* assumes FIQs are enabled, and that the processor is in SVC mode.
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*/
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.macro save_and_disable_irqs, oldcpsr
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#ifdef CONFIG_CPU_V7M
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mrs \oldcpsr, primask
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#else
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mrs \oldcpsr, cpsr
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#endif
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disable_irq
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.endm
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.macro save_and_disable_irqs_notrace, oldcpsr
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#ifdef CONFIG_CPU_V7M
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mrs \oldcpsr, primask
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#else
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mrs \oldcpsr, cpsr
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#endif
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disable_irq_notrace
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.endm
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/*
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* Restore interrupt state previously stored in a register. We don't
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* guarantee that this will preserve the flags.
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*/
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.macro restore_irqs_notrace, oldcpsr
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#ifdef CONFIG_CPU_V7M
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msr primask, \oldcpsr
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#else
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msr cpsr_c, \oldcpsr
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#endif
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.endm
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.macro restore_irqs, oldcpsr
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tst \oldcpsr, #PSR_I_BIT
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asm_trace_hardirqs_on cond=eq
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restore_irqs_notrace \oldcpsr
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.endm
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/*
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* Assembly version of "adr rd, BSYM(sym)". This should only be used to
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* reference local symbols in the same assembly file which are to be
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* resolved by the assembler. Other usage is undefined.
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*/
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.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
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.macro badr\c, rd, sym
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#ifdef CONFIG_THUMB2_KERNEL
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adr\c \rd, \sym + 1
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#else
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adr\c \rd, \sym
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#endif
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.endm
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.endr
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/*
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* Get current thread_info.
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*/
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.macro get_thread_info, rd
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ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT )
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THUMB( mov \rd, sp )
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THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT )
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mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT
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.endm
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/*
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* Increment/decrement the preempt count.
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*/
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#ifdef CONFIG_PREEMPT_COUNT
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.macro inc_preempt_count, ti, tmp
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ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
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add \tmp, \tmp, #1 @ increment it
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str \tmp, [\ti, #TI_PREEMPT]
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.endm
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.macro dec_preempt_count, ti, tmp
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ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
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sub \tmp, \tmp, #1 @ decrement it
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str \tmp, [\ti, #TI_PREEMPT]
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.endm
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.macro dec_preempt_count_ti, ti, tmp
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get_thread_info \ti
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dec_preempt_count \ti, \tmp
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.endm
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#else
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.macro inc_preempt_count, ti, tmp
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.endm
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.macro dec_preempt_count, ti, tmp
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.endm
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.macro dec_preempt_count_ti, ti, tmp
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.endm
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#endif
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#define USERL(l, x...) \
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9999: x; \
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.pushsection __ex_table,"a"; \
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.align 3; \
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.long 9999b,l; \
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.popsection
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#define USER(x...) USERL(9001f, x)
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#ifdef CONFIG_SMP
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#define ALT_SMP(instr...) \
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9998: instr
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/*
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* Note: if you get assembler errors from ALT_UP() when building with
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* CONFIG_THUMB2_KERNEL, you almost certainly need to use
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* ALT_SMP( W(instr) ... )
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*/
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#define ALT_UP(instr...) \
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.pushsection ".alt.smp.init", "a" ;\
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.long 9998b - . ;\
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9997: instr ;\
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.if . - 9997b == 2 ;\
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nop ;\
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.endif ;\
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.if . - 9997b != 4 ;\
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.error "ALT_UP() content must assemble to exactly 4 bytes";\
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.endif ;\
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.popsection
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#define ALT_UP_B(label) \
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.pushsection ".alt.smp.init", "a" ;\
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.long 9998b - . ;\
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W(b) . + (label - 9998b) ;\
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.popsection
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#else
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#define ALT_SMP(instr...)
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#define ALT_UP(instr...) instr
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#define ALT_UP_B(label) b label
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#endif
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/*
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* Instruction barrier
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*/
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.macro instr_sync
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#if __LINUX_ARM_ARCH__ >= 7
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isb
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#elif __LINUX_ARM_ARCH__ == 6
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mcr p15, 0, r0, c7, c5, 4
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#endif
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.endm
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/*
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* SMP data memory barrier
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*/
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.macro smp_dmb mode
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#ifdef CONFIG_SMP
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#if __LINUX_ARM_ARCH__ >= 7
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.ifeqs "\mode","arm"
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ALT_SMP(dmb ish)
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.else
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ALT_SMP(W(dmb) ish)
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.endif
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#elif __LINUX_ARM_ARCH__ == 6
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ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
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#else
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#error Incompatible SMP platform
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#endif
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.ifeqs "\mode","arm"
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ALT_UP(nop)
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.else
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ALT_UP(W(nop))
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.endif
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#endif
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.endm
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#if defined(CONFIG_CPU_V7M)
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/*
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* setmode is used to assert to be in svc mode during boot. For v7-M
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* this is done in __v7m_setup, so setmode can be empty here.
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*/
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.macro setmode, mode, reg
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.endm
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#elif defined(CONFIG_THUMB2_KERNEL)
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.macro setmode, mode, reg
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mov \reg, #\mode
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msr cpsr_c, \reg
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.endm
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#else
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.macro setmode, mode, reg
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msr cpsr_c, #\mode
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.endm
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#endif
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/*
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* Helper macro to enter SVC mode cleanly and mask interrupts. reg is
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* a scratch register for the macro to overwrite.
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*
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* This macro is intended for forcing the CPU into SVC mode at boot time.
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* you cannot return to the original mode.
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*/
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.macro safe_svcmode_maskall reg:req
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#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
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mrs \reg , cpsr
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eor \reg, \reg, #HYP_MODE
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tst \reg, #MODE_MASK
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bic \reg , \reg , #MODE_MASK
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orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
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THUMB( orr \reg , \reg , #PSR_T_BIT )
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bne 1f
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orr \reg, \reg, #PSR_A_BIT
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badr lr, 2f
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msr spsr_cxsf, \reg
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__MSR_ELR_HYP(14)
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__ERET
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1: msr cpsr_c, \reg
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2:
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#else
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/*
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* workaround for possibly broken pre-v6 hardware
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* (akita, Sharp Zaurus C-1000, PXA270-based)
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*/
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setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
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#endif
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.endm
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/*
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* STRT/LDRT access macros with ARM and Thumb-2 variants
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*/
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#ifdef CONFIG_THUMB2_KERNEL
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.macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
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9999:
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.if \inc == 1
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\instr\()b\t\cond\().w \reg, [\ptr, #\off]
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.elseif \inc == 4
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\instr\t\cond\().w \reg, [\ptr, #\off]
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.else
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.error "Unsupported inc macro argument"
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.endif
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.pushsection __ex_table,"a"
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.align 3
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.long 9999b, \abort
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.popsection
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.endm
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.macro usracc, instr, reg, ptr, inc, cond, rept, abort
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@ explicit IT instruction needed because of the label
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@ introduced by the USER macro
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.ifnc \cond,al
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.if \rept == 1
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itt \cond
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.elseif \rept == 2
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ittt \cond
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.else
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.error "Unsupported rept macro argument"
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.endif
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.endif
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@ Slightly optimised to avoid incrementing the pointer twice
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usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
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.if \rept == 2
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usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
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.endif
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add\cond \ptr, #\rept * \inc
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.endm
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#else /* !CONFIG_THUMB2_KERNEL */
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.macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
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.rept \rept
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9999:
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.if \inc == 1
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\instr\()b\t\cond \reg, [\ptr], #\inc
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.elseif \inc == 4
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\instr\t\cond \reg, [\ptr], #\inc
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.else
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.error "Unsupported inc macro argument"
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.endif
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.pushsection __ex_table,"a"
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.align 3
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.long 9999b, \abort
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.popsection
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.endr
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.endm
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#endif /* CONFIG_THUMB2_KERNEL */
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.macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
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usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
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.endm
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.macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
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usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
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.endm
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/* Utility macro for declaring string literals */
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.macro string name:req, string
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.type \name , #object
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\name:
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.asciz "\string"
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.size \name , . - \name
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.endm
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.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
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.macro ret\c, reg
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#if __LINUX_ARM_ARCH__ < 6
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mov\c pc, \reg
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#else
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.ifeqs "\reg", "lr"
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bx\c \reg
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.else
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mov\c pc, \reg
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.endif
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#endif
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.endm
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.endr
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.macro ret.w, reg
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ret \reg
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#ifdef CONFIG_THUMB2_KERNEL
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nop
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#endif
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.endm
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.macro bug, msg, line
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#ifdef CONFIG_THUMB2_KERNEL
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1: .inst 0xde02
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#else
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1: .inst 0xe7f001f2
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#endif
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#ifdef CONFIG_DEBUG_BUGVERBOSE
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.pushsection .rodata.str, "aMS", %progbits, 1
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2: .asciz "\msg"
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.popsection
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.pushsection __bug_table, "aw"
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.align 2
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.word 1b, 2b
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.hword \line
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.popsection
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#endif
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.endm
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#ifdef CONFIG_KPROBES
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#define _ASM_NOKPROBE(entry) \
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.pushsection "_kprobe_blacklist", "aw" ; \
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.balign 4 ; \
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.long entry; \
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.popsection
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#else
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#define _ASM_NOKPROBE(entry)
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#endif
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.macro __adldst_l, op, reg, sym, tmp, c
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.if __LINUX_ARM_ARCH__ < 7
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ldr\c \tmp, .La\@
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.subsection 1
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.align 2
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.La\@: .long \sym - .Lpc\@
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.previous
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.else
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.ifnb \c
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THUMB( ittt \c )
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.endif
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movw\c \tmp, #:lower16:\sym - .Lpc\@
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movt\c \tmp, #:upper16:\sym - .Lpc\@
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.endif
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#ifndef CONFIG_THUMB2_KERNEL
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.set .Lpc\@, . + 8 // PC bias
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.ifc \op, add
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add\c \reg, \tmp, pc
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.else
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\op\c \reg, [pc, \tmp]
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.endif
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#else
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.Lb\@: add\c \tmp, \tmp, pc
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/*
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* In Thumb-2 builds, the PC bias depends on whether we are currently
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* emitting into a .arm or a .thumb section. The size of the add opcode
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* above will be 2 bytes when emitting in Thumb mode and 4 bytes when
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* emitting in ARM mode, so let's use this to account for the bias.
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*/
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.set .Lpc\@, . + (. - .Lb\@)
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.ifnc \op, add
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\op\c \reg, [\tmp]
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.endif
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#endif
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.endm
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/*
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* mov_l - move a constant value or [relocated] address into a register
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*/
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.macro mov_l, dst:req, imm:req
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.if __LINUX_ARM_ARCH__ < 7
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ldr \dst, =\imm
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.else
|
|
movw \dst, #:lower16:\imm
|
|
movt \dst, #:upper16:\imm
|
|
.endif
|
|
.endm
|
|
|
|
/*
|
|
* adr_l - adr pseudo-op with unlimited range
|
|
*
|
|
* @dst: destination register
|
|
* @sym: name of the symbol
|
|
* @cond: conditional opcode suffix
|
|
*/
|
|
.macro adr_l, dst:req, sym:req, cond
|
|
__adldst_l add, \dst, \sym, \dst, \cond
|
|
.endm
|
|
|
|
/*
|
|
* ldr_l - ldr <literal> pseudo-op with unlimited range
|
|
*
|
|
* @dst: destination register
|
|
* @sym: name of the symbol
|
|
* @cond: conditional opcode suffix
|
|
*/
|
|
.macro ldr_l, dst:req, sym:req, cond
|
|
__adldst_l ldr, \dst, \sym, \dst, \cond
|
|
.endm
|
|
|
|
/*
|
|
* str_l - str <literal> pseudo-op with unlimited range
|
|
*
|
|
* @src: source register
|
|
* @sym: name of the symbol
|
|
* @tmp: mandatory scratch register
|
|
* @cond: conditional opcode suffix
|
|
*/
|
|
.macro str_l, src:req, sym:req, tmp:req, cond
|
|
__adldst_l str, \src, \sym, \tmp, \cond
|
|
.endm
|
|
|
|
/*
|
|
* rev_l - byte-swap a 32-bit value
|
|
*
|
|
* @val: source/destination register
|
|
* @tmp: scratch register
|
|
*/
|
|
.macro rev_l, val:req, tmp:req
|
|
.if __LINUX_ARM_ARCH__ < 6
|
|
eor \tmp, \val, \val, ror #16
|
|
bic \tmp, \tmp, #0x00ff0000
|
|
mov \val, \val, ror #8
|
|
eor \val, \val, \tmp, lsr #8
|
|
.else
|
|
rev \val, \val
|
|
.endif
|
|
.endm
|
|
|
|
#endif /* __ASM_ASSEMBLER_H__ */
|