356 lines
10 KiB
C
356 lines
10 KiB
C
/*
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* Copyright (C) 2015 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/**
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* DOC: VC4 HVS module.
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*
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* The Hardware Video Scaler (HVS) is the piece of hardware that does
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* translation, scaling, colorspace conversion, and compositing of
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* pixels stored in framebuffers into a FIFO of pixels going out to
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* the Pixel Valve (CRTC). It operates at the system clock rate (the
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* system audio clock gate, specifically), which is much higher than
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* the pixel clock rate.
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*
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* There is a single global HVS, with multiple output FIFOs that can
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* be consumed by the PVs. This file just manages the resources for
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* the HVS, while the vc4_crtc.c code actually drives HVS setup for
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* each CRTC.
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*/
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#include <drm/drm_atomic_helper.h>
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#include <linux/component.h>
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#include "vc4_drv.h"
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#include "vc4_regs.h"
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static const struct debugfs_reg32 hvs_regs[] = {
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VC4_REG32(SCALER_DISPCTRL),
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VC4_REG32(SCALER_DISPSTAT),
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VC4_REG32(SCALER_DISPID),
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VC4_REG32(SCALER_DISPECTRL),
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VC4_REG32(SCALER_DISPPROF),
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VC4_REG32(SCALER_DISPDITHER),
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VC4_REG32(SCALER_DISPEOLN),
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VC4_REG32(SCALER_DISPLIST0),
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VC4_REG32(SCALER_DISPLIST1),
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VC4_REG32(SCALER_DISPLIST2),
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VC4_REG32(SCALER_DISPLSTAT),
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VC4_REG32(SCALER_DISPLACT0),
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VC4_REG32(SCALER_DISPLACT1),
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VC4_REG32(SCALER_DISPLACT2),
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VC4_REG32(SCALER_DISPCTRL0),
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VC4_REG32(SCALER_DISPBKGND0),
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VC4_REG32(SCALER_DISPSTAT0),
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VC4_REG32(SCALER_DISPBASE0),
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VC4_REG32(SCALER_DISPCTRL1),
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VC4_REG32(SCALER_DISPBKGND1),
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VC4_REG32(SCALER_DISPSTAT1),
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VC4_REG32(SCALER_DISPBASE1),
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VC4_REG32(SCALER_DISPCTRL2),
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VC4_REG32(SCALER_DISPBKGND2),
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VC4_REG32(SCALER_DISPSTAT2),
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VC4_REG32(SCALER_DISPBASE2),
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VC4_REG32(SCALER_DISPALPHA2),
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VC4_REG32(SCALER_OLEDOFFS),
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VC4_REG32(SCALER_OLEDCOEF0),
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VC4_REG32(SCALER_OLEDCOEF1),
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VC4_REG32(SCALER_OLEDCOEF2),
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};
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void vc4_hvs_dump_state(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct drm_printer p = drm_info_printer(&vc4->hvs->pdev->dev);
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int i;
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drm_print_regset32(&p, &vc4->hvs->regset);
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DRM_INFO("HVS ctx:\n");
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for (i = 0; i < 64; i += 4) {
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DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n",
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i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D",
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readl((u32 __iomem *)vc4->hvs->dlist + i + 0),
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readl((u32 __iomem *)vc4->hvs->dlist + i + 1),
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readl((u32 __iomem *)vc4->hvs->dlist + i + 2),
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readl((u32 __iomem *)vc4->hvs->dlist + i + 3));
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}
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}
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static int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = m->private;
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struct drm_device *dev = node->minor->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct drm_printer p = drm_seq_file_printer(m);
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drm_printf(&p, "%d\n", atomic_read(&vc4->underrun));
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return 0;
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}
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/* The filter kernel is composed of dwords each containing 3 9-bit
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* signed integers packed next to each other.
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*/
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#define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff)
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#define VC4_PPF_FILTER_WORD(c0, c1, c2) \
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((((c0) & 0x1ff) << 0) | \
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(((c1) & 0x1ff) << 9) | \
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(((c2) & 0x1ff) << 18))
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/* The whole filter kernel is arranged as the coefficients 0-16 going
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* up, then a pad, then 17-31 going down and reversed within the
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* dwords. This means that a linear phase kernel (where it's
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* symmetrical at the boundary between 15 and 16) has the last 5
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* dwords matching the first 5, but reversed.
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*/
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#define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8, \
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c9, c10, c11, c12, c13, c14, c15) \
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{VC4_PPF_FILTER_WORD(c0, c1, c2), \
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VC4_PPF_FILTER_WORD(c3, c4, c5), \
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VC4_PPF_FILTER_WORD(c6, c7, c8), \
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VC4_PPF_FILTER_WORD(c9, c10, c11), \
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VC4_PPF_FILTER_WORD(c12, c13, c14), \
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VC4_PPF_FILTER_WORD(c15, c15, 0)}
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#define VC4_LINEAR_PHASE_KERNEL_DWORDS 6
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#define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1)
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/* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali.
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* http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf
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*/
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static const u32 mitchell_netravali_1_3_1_3_kernel[] =
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VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18,
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50, 82, 119, 155, 187, 213, 227);
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static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs,
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struct drm_mm_node *space,
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const u32 *kernel)
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{
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int ret, i;
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u32 __iomem *dst_kernel;
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ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS);
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if (ret) {
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DRM_ERROR("Failed to allocate space for filter kernel: %d\n",
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ret);
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return ret;
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}
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dst_kernel = hvs->dlist + space->start;
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for (i = 0; i < VC4_KERNEL_DWORDS; i++) {
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if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS)
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writel(kernel[i], &dst_kernel[i]);
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else {
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writel(kernel[VC4_KERNEL_DWORDS - i - 1],
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&dst_kernel[i]);
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}
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}
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return 0;
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}
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void vc4_hvs_mask_underrun(struct drm_device *dev, int channel)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
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dispctrl &= ~SCALER_DISPCTRL_DSPEISLUR(channel);
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HVS_WRITE(SCALER_DISPCTRL, dispctrl);
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}
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void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
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dispctrl |= SCALER_DISPCTRL_DSPEISLUR(channel);
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HVS_WRITE(SCALER_DISPSTAT,
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SCALER_DISPSTAT_EUFLOW(channel));
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HVS_WRITE(SCALER_DISPCTRL, dispctrl);
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}
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static void vc4_hvs_report_underrun(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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atomic_inc(&vc4->underrun);
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DRM_DEV_ERROR(dev->dev, "HVS underrun\n");
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}
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static irqreturn_t vc4_hvs_irq_handler(int irq, void *data)
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{
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struct drm_device *dev = data;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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irqreturn_t irqret = IRQ_NONE;
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int channel;
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u32 control;
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u32 status;
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status = HVS_READ(SCALER_DISPSTAT);
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control = HVS_READ(SCALER_DISPCTRL);
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for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) {
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/* Interrupt masking is not always honored, so check it here. */
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if (status & SCALER_DISPSTAT_EUFLOW(channel) &&
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control & SCALER_DISPCTRL_DSPEISLUR(channel)) {
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vc4_hvs_mask_underrun(dev, channel);
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vc4_hvs_report_underrun(dev);
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irqret = IRQ_HANDLED;
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}
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}
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/* Clear every per-channel interrupt flag. */
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HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) |
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SCALER_DISPSTAT_IRQMASK(1) |
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SCALER_DISPSTAT_IRQMASK(2));
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return irqret;
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}
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static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct drm_device *drm = dev_get_drvdata(master);
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struct vc4_dev *vc4 = drm->dev_private;
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struct vc4_hvs *hvs = NULL;
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int ret;
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u32 dispctrl;
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hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
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if (!hvs)
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return -ENOMEM;
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hvs->pdev = pdev;
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hvs->regs = vc4_ioremap_regs(pdev, 0);
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if (IS_ERR(hvs->regs))
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return PTR_ERR(hvs->regs);
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hvs->regset.base = hvs->regs;
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hvs->regset.regs = hvs_regs;
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hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
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hvs->dlist = hvs->regs + SCALER_DLIST_START;
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spin_lock_init(&hvs->mm_lock);
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/* Set up the HVS display list memory manager. We never
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* overwrite the setup from the bootloader (just 128b out of
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* our 16K), since we don't want to scramble the screen when
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* transitioning from the firmware's boot setup to runtime.
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*/
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drm_mm_init(&hvs->dlist_mm,
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HVS_BOOTLOADER_DLIST_END,
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(SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END);
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/* Set up the HVS LBM memory manager. We could have some more
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* complicated data structure that allowed reuse of LBM areas
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* between planes when they don't overlap on the screen, but
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* for now we just allocate globally.
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*/
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drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
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/* Upload filter kernels. We only have the one for now, so we
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* keep it around for the lifetime of the driver.
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*/
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ret = vc4_hvs_upload_linear_kernel(hvs,
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&hvs->mitchell_netravali_filter,
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mitchell_netravali_1_3_1_3_kernel);
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if (ret)
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return ret;
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vc4->hvs = hvs;
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dispctrl = HVS_READ(SCALER_DISPCTRL);
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dispctrl |= SCALER_DISPCTRL_ENABLE;
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dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) |
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SCALER_DISPCTRL_DISPEIRQ(1) |
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SCALER_DISPCTRL_DISPEIRQ(2);
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/* Set DSP3 (PV1) to use HVS channel 2, which would otherwise
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* be unused.
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*/
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dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
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dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
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SCALER_DISPCTRL_SLVWREIRQ |
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SCALER_DISPCTRL_SLVRDEIRQ |
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SCALER_DISPCTRL_DSPEIEOF(0) |
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SCALER_DISPCTRL_DSPEIEOF(1) |
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SCALER_DISPCTRL_DSPEIEOF(2) |
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SCALER_DISPCTRL_DSPEIEOLN(0) |
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SCALER_DISPCTRL_DSPEIEOLN(1) |
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SCALER_DISPCTRL_DSPEIEOLN(2) |
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SCALER_DISPCTRL_DSPEISLUR(0) |
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SCALER_DISPCTRL_DSPEISLUR(1) |
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SCALER_DISPCTRL_DSPEISLUR(2) |
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SCALER_DISPCTRL_SCLEIRQ);
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dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
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HVS_WRITE(SCALER_DISPCTRL, dispctrl);
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ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
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vc4_hvs_irq_handler, 0, "vc4 hvs", drm);
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if (ret)
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return ret;
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vc4_debugfs_add_regset32(drm, "hvs_regs", &hvs->regset);
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vc4_debugfs_add_file(drm, "hvs_underrun", vc4_hvs_debugfs_underrun,
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NULL);
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return 0;
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}
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static void vc4_hvs_unbind(struct device *dev, struct device *master,
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void *data)
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{
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struct drm_device *drm = dev_get_drvdata(master);
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struct vc4_dev *vc4 = drm->dev_private;
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if (vc4->hvs->mitchell_netravali_filter.allocated)
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drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter);
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drm_mm_takedown(&vc4->hvs->dlist_mm);
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drm_mm_takedown(&vc4->hvs->lbm_mm);
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vc4->hvs = NULL;
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}
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static const struct component_ops vc4_hvs_ops = {
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.bind = vc4_hvs_bind,
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.unbind = vc4_hvs_unbind,
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};
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static int vc4_hvs_dev_probe(struct platform_device *pdev)
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{
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return component_add(&pdev->dev, &vc4_hvs_ops);
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}
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static int vc4_hvs_dev_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &vc4_hvs_ops);
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return 0;
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}
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static const struct of_device_id vc4_hvs_dt_match[] = {
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{ .compatible = "brcm,bcm2835-hvs" },
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{}
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};
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struct platform_driver vc4_hvs_driver = {
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.probe = vc4_hvs_dev_probe,
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.remove = vc4_hvs_dev_remove,
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.driver = {
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.name = "vc4_hvs",
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.of_match_table = vc4_hvs_dt_match,
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},
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};
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