263 lines
6.8 KiB
C
263 lines
6.8 KiB
C
/*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2006 Atmark Techno, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/interrupt.h>
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#include <linux/profile.h>
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#include <linux/irq.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <asm/cpuinfo.h>
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#include <asm/setup.h>
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#include <asm/prom.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#ifdef CONFIG_SELFMOD_TIMER
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#include <asm/selfmod.h>
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#define TIMER_BASE BARRIER_BASE_ADDR
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#else
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static unsigned int timer_baseaddr;
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#define TIMER_BASE timer_baseaddr
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#endif
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#define TCSR0 (0x00)
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#define TLR0 (0x04)
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#define TCR0 (0x08)
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#define TCSR1 (0x10)
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#define TLR1 (0x14)
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#define TCR1 (0x18)
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#define TCSR_MDT (1<<0)
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#define TCSR_UDT (1<<1)
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#define TCSR_GENT (1<<2)
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#define TCSR_CAPT (1<<3)
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#define TCSR_ARHT (1<<4)
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#define TCSR_LOAD (1<<5)
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#define TCSR_ENIT (1<<6)
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#define TCSR_ENT (1<<7)
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#define TCSR_TINT (1<<8)
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#define TCSR_PWMA (1<<9)
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#define TCSR_ENALL (1<<10)
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static inline void microblaze_timer0_stop(void)
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{
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out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT);
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}
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static inline void microblaze_timer0_start_periodic(unsigned long load_val)
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{
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if (!load_val)
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load_val = 1;
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out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
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/* load the initial value */
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out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
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/* see timer data sheet for detail
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* !ENALL - don't enable 'em all
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* !PWMA - disable pwm
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* TINT - clear interrupt status
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* ENT- enable timer itself
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* EINT - enable interrupt
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* !LOAD - clear the bit to let go
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* ARHT - auto reload
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* !CAPT - no external trigger
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* !GENT - no external signal
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* UDT - set the timer as down counter
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* !MDT0 - generate mode
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*/
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out_be32(TIMER_BASE + TCSR0,
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TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
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}
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static inline void microblaze_timer0_start_oneshot(unsigned long load_val)
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{
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if (!load_val)
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load_val = 1;
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out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
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/* load the initial value */
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out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
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out_be32(TIMER_BASE + TCSR0,
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TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
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}
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static int microblaze_timer_set_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
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microblaze_timer0_start_oneshot(delta);
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return 0;
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}
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static void microblaze_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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printk(KERN_INFO "%s: periodic\n", __func__);
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microblaze_timer0_start_periodic(cpuinfo.freq_div_hz);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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printk(KERN_INFO "%s: oneshot\n", __func__);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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printk(KERN_INFO "%s: unused\n", __func__);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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printk(KERN_INFO "%s: shutdown\n", __func__);
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microblaze_timer0_stop();
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break;
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case CLOCK_EVT_MODE_RESUME:
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printk(KERN_INFO "%s: resume\n", __func__);
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break;
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}
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}
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static struct clock_event_device clockevent_microblaze_timer = {
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.name = "microblaze_clockevent",
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.shift = 24,
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.rating = 300,
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.set_next_event = microblaze_timer_set_next_event,
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.set_mode = microblaze_timer_set_mode,
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};
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static inline void timer_ack(void)
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{
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out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0));
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}
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &clockevent_microblaze_timer;
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#ifdef CONFIG_HEART_BEAT
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heartbeat();
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#endif
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timer_ack();
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction timer_irqaction = {
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.handler = timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.name = "timer",
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.dev_id = &clockevent_microblaze_timer,
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};
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static __init void microblaze_clockevent_init(void)
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{
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clockevent_microblaze_timer.mult =
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div_sc(cpuinfo.cpu_clock_freq, NSEC_PER_SEC,
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clockevent_microblaze_timer.shift);
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clockevent_microblaze_timer.max_delta_ns =
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clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer);
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clockevent_microblaze_timer.min_delta_ns =
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clockevent_delta2ns(1, &clockevent_microblaze_timer);
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clockevent_microblaze_timer.cpumask = cpumask_of(0);
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clockevents_register_device(&clockevent_microblaze_timer);
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}
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static cycle_t microblaze_read(struct clocksource *cs)
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{
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/* reading actual value of timer 1 */
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return (cycle_t) (in_be32(TIMER_BASE + TCR1));
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}
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static struct clocksource clocksource_microblaze = {
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.name = "microblaze_clocksource",
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.rating = 300,
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.read = microblaze_read,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 24, /* I can shift it */
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init microblaze_clocksource_init(void)
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{
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clocksource_microblaze.mult =
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clocksource_hz2mult(cpuinfo.cpu_clock_freq,
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clocksource_microblaze.shift);
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if (clocksource_register(&clocksource_microblaze))
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panic("failed to register clocksource");
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/* stop timer1 */
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out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT);
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/* start timer1 - up counting without interrupt */
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out_be32(TIMER_BASE + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);
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return 0;
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}
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void __init time_init(void)
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{
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u32 irq, i = 0;
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u32 timer_num = 1;
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struct device_node *timer = NULL;
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#ifdef CONFIG_SELFMOD_TIMER
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unsigned int timer_baseaddr = 0;
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int arr_func[] = {
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(int)µblaze_read,
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(int)&timer_interrupt,
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(int)µblaze_clocksource_init,
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(int)µblaze_timer_set_mode,
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(int)µblaze_timer_set_next_event,
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0
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};
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#endif
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char *timer_list[] = {
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"xlnx,xps-timer-1.00.a",
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"xlnx,opb-timer-1.00.b",
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"xlnx,opb-timer-1.00.a",
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NULL
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};
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for (i = 0; timer_list[i] != NULL; i++) {
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timer = of_find_compatible_node(NULL, NULL, timer_list[i]);
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if (timer)
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break;
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}
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timer_baseaddr = *(int *) of_get_property(timer, "reg", NULL);
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timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE);
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irq = *(int *) of_get_property(timer, "interrupts", NULL);
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timer_num =
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*(int *) of_get_property(timer, "xlnx,one-timer-only", NULL);
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if (timer_num) {
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printk(KERN_EMERG "Please enable two timers in HW\n");
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BUG();
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}
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#ifdef CONFIG_SELFMOD_TIMER
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selfmod_function((int *) arr_func, timer_baseaddr);
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#endif
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printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n",
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timer_list[i], timer_baseaddr, irq);
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cpuinfo.freq_div_hz = cpuinfo.cpu_clock_freq / HZ;
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setup_irq(irq, &timer_irqaction);
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#ifdef CONFIG_HEART_BEAT
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setup_heartbeat();
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#endif
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microblaze_clocksource_init();
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microblaze_clockevent_init();
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}
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