858 lines
26 KiB
C
858 lines
26 KiB
C
/*
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* Netburst Perfomance Events (P4, old Xeon)
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*
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* Copyright (C) 2010 Parallels, Inc., Cyrill Gorcunov <gorcunov@openvz.org>
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* Copyright (C) 2010 Intel Corporation, Lin Ming <ming.m.lin@intel.com>
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*
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* For licencing details see kernel-base/COPYING
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*/
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#ifdef CONFIG_CPU_SUP_INTEL
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#include <asm/perf_event_p4.h>
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#define P4_CNTR_LIMIT 3
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/*
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* array indices: 0,1 - HT threads, used with HT enabled cpu
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*/
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struct p4_event_bind {
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unsigned int opcode; /* Event code and ESCR selector */
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unsigned int escr_msr[2]; /* ESCR MSR for this event */
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char cntr[2][P4_CNTR_LIMIT]; /* counter index (offset), -1 on abscence */
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};
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struct p4_cache_event_bind {
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unsigned int metric_pebs;
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unsigned int metric_vert;
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};
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#define P4_GEN_CACHE_EVENT_BIND(name) \
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[P4_CACHE__##name] = { \
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.metric_pebs = P4_PEBS__##name, \
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.metric_vert = P4_VERT__##name, \
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}
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static struct p4_cache_event_bind p4_cache_event_bind_map[] = {
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P4_GEN_CACHE_EVENT_BIND(1stl_cache_load_miss_retired),
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P4_GEN_CACHE_EVENT_BIND(2ndl_cache_load_miss_retired),
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P4_GEN_CACHE_EVENT_BIND(dtlb_load_miss_retired),
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P4_GEN_CACHE_EVENT_BIND(dtlb_store_miss_retired),
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};
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/*
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* Note that we don't use CCCR1 here, there is an
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* exception for P4_BSQ_ALLOCATION but we just have
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* no workaround
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*
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* consider this binding as resources which particular
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* event may borrow, it doesn't contain EventMask,
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* Tags and friends -- they are left to a caller
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*/
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static struct p4_event_bind p4_event_bind_map[] = {
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[P4_EVENT_TC_DELIVER_MODE] = {
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.opcode = P4_OPCODE(P4_EVENT_TC_DELIVER_MODE),
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.escr_msr = { MSR_P4_TC_ESCR0, MSR_P4_TC_ESCR1 },
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.cntr = { {4, 5, -1}, {6, 7, -1} },
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},
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[P4_EVENT_BPU_FETCH_REQUEST] = {
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.opcode = P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST),
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.escr_msr = { MSR_P4_BPU_ESCR0, MSR_P4_BPU_ESCR1 },
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.cntr = { {0, -1, -1}, {2, -1, -1} },
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},
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[P4_EVENT_ITLB_REFERENCE] = {
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.opcode = P4_OPCODE(P4_EVENT_ITLB_REFERENCE),
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.escr_msr = { MSR_P4_ITLB_ESCR0, MSR_P4_ITLB_ESCR1 },
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.cntr = { {0, -1, -1}, {2, -1, -1} },
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},
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[P4_EVENT_MEMORY_CANCEL] = {
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.opcode = P4_OPCODE(P4_EVENT_MEMORY_CANCEL),
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.escr_msr = { MSR_P4_DAC_ESCR0, MSR_P4_DAC_ESCR1 },
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.cntr = { {8, 9, -1}, {10, 11, -1} },
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},
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[P4_EVENT_MEMORY_COMPLETE] = {
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.opcode = P4_OPCODE(P4_EVENT_MEMORY_COMPLETE),
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.escr_msr = { MSR_P4_SAAT_ESCR0 , MSR_P4_SAAT_ESCR1 },
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.cntr = { {8, 9, -1}, {10, 11, -1} },
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},
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[P4_EVENT_LOAD_PORT_REPLAY] = {
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.opcode = P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY),
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.escr_msr = { MSR_P4_SAAT_ESCR0, MSR_P4_SAAT_ESCR1 },
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.cntr = { {8, 9, -1}, {10, 11, -1} },
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},
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[P4_EVENT_STORE_PORT_REPLAY] = {
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.opcode = P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY),
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.escr_msr = { MSR_P4_SAAT_ESCR0 , MSR_P4_SAAT_ESCR1 },
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.cntr = { {8, 9, -1}, {10, 11, -1} },
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},
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[P4_EVENT_MOB_LOAD_REPLAY] = {
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.opcode = P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY),
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.escr_msr = { MSR_P4_MOB_ESCR0, MSR_P4_MOB_ESCR1 },
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.cntr = { {0, -1, -1}, {2, -1, -1} },
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},
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[P4_EVENT_PAGE_WALK_TYPE] = {
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.opcode = P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE),
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.escr_msr = { MSR_P4_PMH_ESCR0, MSR_P4_PMH_ESCR1 },
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.cntr = { {0, -1, -1}, {2, -1, -1} },
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},
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[P4_EVENT_BSQ_CACHE_REFERENCE] = {
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.opcode = P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE),
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.escr_msr = { MSR_P4_BSU_ESCR0, MSR_P4_BSU_ESCR1 },
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.cntr = { {0, -1, -1}, {2, -1, -1} },
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},
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[P4_EVENT_IOQ_ALLOCATION] = {
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.opcode = P4_OPCODE(P4_EVENT_IOQ_ALLOCATION),
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.escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
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.cntr = { {0, -1, -1}, {2, -1, -1} },
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},
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[P4_EVENT_IOQ_ACTIVE_ENTRIES] = { /* shared ESCR */
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.opcode = P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES),
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.escr_msr = { MSR_P4_FSB_ESCR1, MSR_P4_FSB_ESCR1 },
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.cntr = { {2, -1, -1}, {3, -1, -1} },
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},
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[P4_EVENT_FSB_DATA_ACTIVITY] = {
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.opcode = P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY),
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.escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
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.cntr = { {0, -1, -1}, {2, -1, -1} },
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},
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[P4_EVENT_BSQ_ALLOCATION] = { /* shared ESCR, broken CCCR1 */
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.opcode = P4_OPCODE(P4_EVENT_BSQ_ALLOCATION),
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.escr_msr = { MSR_P4_BSU_ESCR0, MSR_P4_BSU_ESCR0 },
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.cntr = { {0, -1, -1}, {1, -1, -1} },
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},
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[P4_EVENT_BSQ_ACTIVE_ENTRIES] = { /* shared ESCR */
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.opcode = P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES),
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.escr_msr = { MSR_P4_BSU_ESCR1 , MSR_P4_BSU_ESCR1 },
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.cntr = { {2, -1, -1}, {3, -1, -1} },
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},
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[P4_EVENT_SSE_INPUT_ASSIST] = {
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.opcode = P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST),
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.escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
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.cntr = { {8, 9, -1}, {10, 11, -1} },
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},
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[P4_EVENT_PACKED_SP_UOP] = {
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.opcode = P4_OPCODE(P4_EVENT_PACKED_SP_UOP),
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.escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
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.cntr = { {8, 9, -1}, {10, 11, -1} },
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},
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[P4_EVENT_PACKED_DP_UOP] = {
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.opcode = P4_OPCODE(P4_EVENT_PACKED_DP_UOP),
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.escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
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.cntr = { {8, 9, -1}, {10, 11, -1} },
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},
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[P4_EVENT_SCALAR_SP_UOP] = {
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.opcode = P4_OPCODE(P4_EVENT_SCALAR_SP_UOP),
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.escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
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.cntr = { {8, 9, -1}, {10, 11, -1} },
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},
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[P4_EVENT_SCALAR_DP_UOP] = {
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.opcode = P4_OPCODE(P4_EVENT_SCALAR_DP_UOP),
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.escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
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.cntr = { {8, 9, -1}, {10, 11, -1} },
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},
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[P4_EVENT_64BIT_MMX_UOP] = {
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.opcode = P4_OPCODE(P4_EVENT_64BIT_MMX_UOP),
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.escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
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.cntr = { {8, 9, -1}, {10, 11, -1} },
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},
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[P4_EVENT_128BIT_MMX_UOP] = {
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.opcode = P4_OPCODE(P4_EVENT_128BIT_MMX_UOP),
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.escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
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.cntr = { {8, 9, -1}, {10, 11, -1} },
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},
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[P4_EVENT_X87_FP_UOP] = {
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.opcode = P4_OPCODE(P4_EVENT_X87_FP_UOP),
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.escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
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.cntr = { {8, 9, -1}, {10, 11, -1} },
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},
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[P4_EVENT_TC_MISC] = {
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.opcode = P4_OPCODE(P4_EVENT_TC_MISC),
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.escr_msr = { MSR_P4_TC_ESCR0, MSR_P4_TC_ESCR1 },
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.cntr = { {4, 5, -1}, {6, 7, -1} },
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},
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[P4_EVENT_GLOBAL_POWER_EVENTS] = {
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.opcode = P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS),
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.escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
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.cntr = { {0, -1, -1}, {2, -1, -1} },
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},
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[P4_EVENT_TC_MS_XFER] = {
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.opcode = P4_OPCODE(P4_EVENT_TC_MS_XFER),
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.escr_msr = { MSR_P4_MS_ESCR0, MSR_P4_MS_ESCR1 },
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.cntr = { {4, 5, -1}, {6, 7, -1} },
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},
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[P4_EVENT_UOP_QUEUE_WRITES] = {
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.opcode = P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES),
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.escr_msr = { MSR_P4_MS_ESCR0, MSR_P4_MS_ESCR1 },
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.cntr = { {4, 5, -1}, {6, 7, -1} },
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},
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[P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE] = {
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.opcode = P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE),
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.escr_msr = { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR0 },
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.cntr = { {4, 5, -1}, {6, 7, -1} },
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},
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[P4_EVENT_RETIRED_BRANCH_TYPE] = {
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.opcode = P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE),
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.escr_msr = { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR1 },
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.cntr = { {4, 5, -1}, {6, 7, -1} },
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},
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[P4_EVENT_RESOURCE_STALL] = {
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.opcode = P4_OPCODE(P4_EVENT_RESOURCE_STALL),
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.escr_msr = { MSR_P4_ALF_ESCR0, MSR_P4_ALF_ESCR1 },
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.cntr = { {12, 13, 16}, {14, 15, 17} },
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},
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[P4_EVENT_WC_BUFFER] = {
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.opcode = P4_OPCODE(P4_EVENT_WC_BUFFER),
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.escr_msr = { MSR_P4_DAC_ESCR0, MSR_P4_DAC_ESCR1 },
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.cntr = { {8, 9, -1}, {10, 11, -1} },
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},
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[P4_EVENT_B2B_CYCLES] = {
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.opcode = P4_OPCODE(P4_EVENT_B2B_CYCLES),
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.escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
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.cntr = { {0, -1, -1}, {2, -1, -1} },
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},
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[P4_EVENT_BNR] = {
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.opcode = P4_OPCODE(P4_EVENT_BNR),
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.escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
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.cntr = { {0, -1, -1}, {2, -1, -1} },
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},
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[P4_EVENT_SNOOP] = {
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.opcode = P4_OPCODE(P4_EVENT_SNOOP),
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.escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
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.cntr = { {0, -1, -1}, {2, -1, -1} },
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},
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[P4_EVENT_RESPONSE] = {
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.opcode = P4_OPCODE(P4_EVENT_RESPONSE),
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.escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
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.cntr = { {0, -1, -1}, {2, -1, -1} },
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},
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[P4_EVENT_FRONT_END_EVENT] = {
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.opcode = P4_OPCODE(P4_EVENT_FRONT_END_EVENT),
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.escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
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.cntr = { {12, 13, 16}, {14, 15, 17} },
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},
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[P4_EVENT_EXECUTION_EVENT] = {
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.opcode = P4_OPCODE(P4_EVENT_EXECUTION_EVENT),
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.escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
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.cntr = { {12, 13, 16}, {14, 15, 17} },
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},
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[P4_EVENT_REPLAY_EVENT] = {
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.opcode = P4_OPCODE(P4_EVENT_REPLAY_EVENT),
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.escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
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.cntr = { {12, 13, 16}, {14, 15, 17} },
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},
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[P4_EVENT_INSTR_RETIRED] = {
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.opcode = P4_OPCODE(P4_EVENT_INSTR_RETIRED),
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.escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
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.cntr = { {12, 13, 16}, {14, 15, 17} },
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},
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[P4_EVENT_UOPS_RETIRED] = {
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.opcode = P4_OPCODE(P4_EVENT_UOPS_RETIRED),
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.escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
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.cntr = { {12, 13, 16}, {14, 15, 17} },
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},
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[P4_EVENT_UOP_TYPE] = {
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.opcode = P4_OPCODE(P4_EVENT_UOP_TYPE),
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.escr_msr = { MSR_P4_RAT_ESCR0, MSR_P4_RAT_ESCR1 },
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.cntr = { {12, 13, 16}, {14, 15, 17} },
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},
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[P4_EVENT_BRANCH_RETIRED] = {
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.opcode = P4_OPCODE(P4_EVENT_BRANCH_RETIRED),
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.escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
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.cntr = { {12, 13, 16}, {14, 15, 17} },
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},
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[P4_EVENT_MISPRED_BRANCH_RETIRED] = {
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.opcode = P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED),
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.escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
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.cntr = { {12, 13, 16}, {14, 15, 17} },
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},
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[P4_EVENT_X87_ASSIST] = {
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.opcode = P4_OPCODE(P4_EVENT_X87_ASSIST),
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.escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
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.cntr = { {12, 13, 16}, {14, 15, 17} },
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},
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[P4_EVENT_MACHINE_CLEAR] = {
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.opcode = P4_OPCODE(P4_EVENT_MACHINE_CLEAR),
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.escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
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.cntr = { {12, 13, 16}, {14, 15, 17} },
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},
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[P4_EVENT_INSTR_COMPLETED] = {
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.opcode = P4_OPCODE(P4_EVENT_INSTR_COMPLETED),
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.escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
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.cntr = { {12, 13, 16}, {14, 15, 17} },
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},
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};
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#define P4_GEN_CACHE_EVENT(event, bit, cache_event) \
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p4_config_pack_escr(P4_ESCR_EVENT(event) | \
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P4_ESCR_EMASK_BIT(event, bit)) | \
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p4_config_pack_cccr(cache_event | \
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P4_CCCR_ESEL(P4_OPCODE_ESEL(P4_OPCODE(event))))
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static __initconst const u64 p4_hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(L1D ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
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P4_CACHE__1stl_cache_load_miss_retired),
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},
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},
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[ C(LL ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
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P4_CACHE__2ndl_cache_load_miss_retired),
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},
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},
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[ C(DTLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
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P4_CACHE__dtlb_load_miss_retired),
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
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P4_CACHE__dtlb_store_miss_retired),
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},
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},
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[ C(ITLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, HIT,
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P4_CACHE__itlb_reference_hit),
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[ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, MISS,
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P4_CACHE__itlb_reference_miss),
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
},
|
|
};
|
|
|
|
static u64 p4_general_events[PERF_COUNT_HW_MAX] = {
|
|
/* non-halted CPU clocks */
|
|
[PERF_COUNT_HW_CPU_CYCLES] =
|
|
p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_GLOBAL_POWER_EVENTS) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING)),
|
|
|
|
/*
|
|
* retired instructions
|
|
* in a sake of simplicity we don't use the FSB tagging
|
|
*/
|
|
[PERF_COUNT_HW_INSTRUCTIONS] =
|
|
p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_INSTR_RETIRED) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, BOGUSNTAG)),
|
|
|
|
/* cache hits */
|
|
[PERF_COUNT_HW_CACHE_REFERENCES] =
|
|
p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_BSQ_CACHE_REFERENCE) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM)),
|
|
|
|
/* cache misses */
|
|
[PERF_COUNT_HW_CACHE_MISSES] =
|
|
p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_BSQ_CACHE_REFERENCE) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS)),
|
|
|
|
/* branch instructions retired */
|
|
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =
|
|
p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_RETIRED_BRANCH_TYPE) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CALL) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT)),
|
|
|
|
/* mispredicted branches retired */
|
|
[PERF_COUNT_HW_BRANCH_MISSES] =
|
|
p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_MISPRED_BRANCH_RETIRED) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS)),
|
|
|
|
/* bus ready clocks (cpu is driving #DRDY_DRV\#DRDY_OWN): */
|
|
[PERF_COUNT_HW_BUS_CYCLES] =
|
|
p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_FSB_DATA_ACTIVITY) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV) |
|
|
P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN)) |
|
|
p4_config_pack_cccr(P4_CCCR_EDGE | P4_CCCR_COMPARE),
|
|
};
|
|
|
|
static struct p4_event_bind *p4_config_get_bind(u64 config)
|
|
{
|
|
unsigned int evnt = p4_config_unpack_event(config);
|
|
struct p4_event_bind *bind = NULL;
|
|
|
|
if (evnt < ARRAY_SIZE(p4_event_bind_map))
|
|
bind = &p4_event_bind_map[evnt];
|
|
|
|
return bind;
|
|
}
|
|
|
|
static u64 p4_pmu_event_map(int hw_event)
|
|
{
|
|
struct p4_event_bind *bind;
|
|
unsigned int esel;
|
|
u64 config;
|
|
|
|
config = p4_general_events[hw_event];
|
|
bind = p4_config_get_bind(config);
|
|
esel = P4_OPCODE_ESEL(bind->opcode);
|
|
config |= p4_config_pack_cccr(P4_CCCR_ESEL(esel));
|
|
|
|
return config;
|
|
}
|
|
|
|
static int p4_hw_config(struct perf_event *event)
|
|
{
|
|
int cpu = get_cpu();
|
|
int rc = 0;
|
|
unsigned int evnt;
|
|
u32 escr, cccr;
|
|
|
|
/*
|
|
* the reason we use cpu that early is that: if we get scheduled
|
|
* first time on the same cpu -- we will not need swap thread
|
|
* specific flags in config (and will save some cpu cycles)
|
|
*/
|
|
|
|
cccr = p4_default_cccr_conf(cpu);
|
|
escr = p4_default_escr_conf(cpu, event->attr.exclude_kernel,
|
|
event->attr.exclude_user);
|
|
event->hw.config = p4_config_pack_escr(escr) |
|
|
p4_config_pack_cccr(cccr);
|
|
|
|
if (p4_ht_active() && p4_ht_thread(cpu))
|
|
event->hw.config = p4_set_ht_bit(event->hw.config);
|
|
|
|
if (event->attr.type == PERF_TYPE_RAW) {
|
|
|
|
/* user data may have out-of-bound event index */
|
|
evnt = p4_config_unpack_event(event->attr.config);
|
|
if (evnt >= ARRAY_SIZE(p4_event_bind_map)) {
|
|
rc = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* We don't control raw events so it's up to the caller
|
|
* to pass sane values (and we don't count the thread number
|
|
* on HT machine but allow HT-compatible specifics to be
|
|
* passed on)
|
|
*
|
|
* XXX: HT wide things should check perf_paranoid_cpu() &&
|
|
* CAP_SYS_ADMIN
|
|
*/
|
|
event->hw.config |= event->attr.config &
|
|
(p4_config_pack_escr(P4_ESCR_MASK_HT) |
|
|
p4_config_pack_cccr(P4_CCCR_MASK_HT));
|
|
}
|
|
|
|
rc = x86_setup_perfctr(event);
|
|
out:
|
|
put_cpu();
|
|
return rc;
|
|
}
|
|
|
|
static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
|
|
{
|
|
int overflow = 0;
|
|
u32 low, high;
|
|
|
|
rdmsr(hwc->config_base + hwc->idx, low, high);
|
|
|
|
/* we need to check high bit for unflagged overflows */
|
|
if ((low & P4_CCCR_OVF) || (high & (1 << 31))) {
|
|
overflow = 1;
|
|
(void)checking_wrmsrl(hwc->config_base + hwc->idx,
|
|
((u64)low) & ~P4_CCCR_OVF);
|
|
}
|
|
|
|
return overflow;
|
|
}
|
|
|
|
static inline void p4_pmu_disable_event(struct perf_event *event)
|
|
{
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
/*
|
|
* If event gets disabled while counter is in overflowed
|
|
* state we need to clear P4_CCCR_OVF, otherwise interrupt get
|
|
* asserted again and again
|
|
*/
|
|
(void)checking_wrmsrl(hwc->config_base + hwc->idx,
|
|
(u64)(p4_config_unpack_cccr(hwc->config)) &
|
|
~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED);
|
|
}
|
|
|
|
static void p4_pmu_disable_all(void)
|
|
{
|
|
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
|
int idx;
|
|
|
|
for (idx = 0; idx < x86_pmu.num_counters; idx++) {
|
|
struct perf_event *event = cpuc->events[idx];
|
|
if (!test_bit(idx, cpuc->active_mask))
|
|
continue;
|
|
p4_pmu_disable_event(event);
|
|
}
|
|
}
|
|
|
|
static void p4_pmu_enable_event(struct perf_event *event)
|
|
{
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
int thread = p4_ht_config_thread(hwc->config);
|
|
u64 escr_conf = p4_config_unpack_escr(p4_clear_ht_bit(hwc->config));
|
|
unsigned int idx = p4_config_unpack_event(hwc->config);
|
|
unsigned int idx_cache = p4_config_unpack_cache_event(hwc->config);
|
|
struct p4_event_bind *bind;
|
|
struct p4_cache_event_bind *bind_cache;
|
|
u64 escr_addr, cccr;
|
|
|
|
bind = &p4_event_bind_map[idx];
|
|
escr_addr = (u64)bind->escr_msr[thread];
|
|
|
|
/*
|
|
* - we dont support cascaded counters yet
|
|
* - and counter 1 is broken (erratum)
|
|
*/
|
|
WARN_ON_ONCE(p4_is_event_cascaded(hwc->config));
|
|
WARN_ON_ONCE(hwc->idx == 1);
|
|
|
|
/* we need a real Event value */
|
|
escr_conf &= ~P4_ESCR_EVENT_MASK;
|
|
escr_conf |= P4_ESCR_EVENT(P4_OPCODE_EVNT(bind->opcode));
|
|
|
|
cccr = p4_config_unpack_cccr(hwc->config);
|
|
|
|
/*
|
|
* it could be Cache event so that we need to
|
|
* set metrics into additional MSRs
|
|
*/
|
|
BUILD_BUG_ON(P4_CACHE__MAX > P4_CCCR_CACHE_OPS_MASK);
|
|
if (idx_cache > P4_CACHE__NONE &&
|
|
idx_cache < ARRAY_SIZE(p4_cache_event_bind_map)) {
|
|
bind_cache = &p4_cache_event_bind_map[idx_cache];
|
|
(void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE, (u64)bind_cache->metric_pebs);
|
|
(void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT, (u64)bind_cache->metric_vert);
|
|
}
|
|
|
|
(void)checking_wrmsrl(escr_addr, escr_conf);
|
|
(void)checking_wrmsrl(hwc->config_base + hwc->idx,
|
|
(cccr & ~P4_CCCR_RESERVED) | P4_CCCR_ENABLE);
|
|
}
|
|
|
|
static void p4_pmu_enable_all(int added)
|
|
{
|
|
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
|
int idx;
|
|
|
|
for (idx = 0; idx < x86_pmu.num_counters; idx++) {
|
|
struct perf_event *event = cpuc->events[idx];
|
|
if (!test_bit(idx, cpuc->active_mask))
|
|
continue;
|
|
p4_pmu_enable_event(event);
|
|
}
|
|
}
|
|
|
|
static int p4_pmu_handle_irq(struct pt_regs *regs)
|
|
{
|
|
struct perf_sample_data data;
|
|
struct cpu_hw_events *cpuc;
|
|
struct perf_event *event;
|
|
struct hw_perf_event *hwc;
|
|
int idx, handled = 0;
|
|
u64 val;
|
|
|
|
data.addr = 0;
|
|
data.raw = NULL;
|
|
|
|
cpuc = &__get_cpu_var(cpu_hw_events);
|
|
|
|
for (idx = 0; idx < x86_pmu.num_counters; idx++) {
|
|
|
|
if (!test_bit(idx, cpuc->active_mask))
|
|
continue;
|
|
|
|
event = cpuc->events[idx];
|
|
hwc = &event->hw;
|
|
|
|
WARN_ON_ONCE(hwc->idx != idx);
|
|
|
|
/* it might be unflagged overflow */
|
|
handled = p4_pmu_clear_cccr_ovf(hwc);
|
|
|
|
val = x86_perf_event_update(event);
|
|
if (!handled && (val & (1ULL << (x86_pmu.cntval_bits - 1))))
|
|
continue;
|
|
|
|
/* event overflow for sure */
|
|
data.period = event->hw.last_period;
|
|
|
|
if (!x86_perf_event_set_period(event))
|
|
continue;
|
|
if (perf_event_overflow(event, 1, &data, regs))
|
|
p4_pmu_disable_event(event);
|
|
}
|
|
|
|
if (handled) {
|
|
/* p4 quirk: unmask it again */
|
|
apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
|
|
inc_irq_stat(apic_perf_irqs);
|
|
}
|
|
|
|
return handled;
|
|
}
|
|
|
|
/*
|
|
* swap thread specific fields according to a thread
|
|
* we are going to run on
|
|
*/
|
|
static void p4_pmu_swap_config_ts(struct hw_perf_event *hwc, int cpu)
|
|
{
|
|
u32 escr, cccr;
|
|
|
|
/*
|
|
* we either lucky and continue on same cpu or no HT support
|
|
*/
|
|
if (!p4_should_swap_ts(hwc->config, cpu))
|
|
return;
|
|
|
|
/*
|
|
* the event is migrated from an another logical
|
|
* cpu, so we need to swap thread specific flags
|
|
*/
|
|
|
|
escr = p4_config_unpack_escr(hwc->config);
|
|
cccr = p4_config_unpack_cccr(hwc->config);
|
|
|
|
if (p4_ht_thread(cpu)) {
|
|
cccr &= ~P4_CCCR_OVF_PMI_T0;
|
|
cccr |= P4_CCCR_OVF_PMI_T1;
|
|
if (escr & P4_ESCR_T0_OS) {
|
|
escr &= ~P4_ESCR_T0_OS;
|
|
escr |= P4_ESCR_T1_OS;
|
|
}
|
|
if (escr & P4_ESCR_T0_USR) {
|
|
escr &= ~P4_ESCR_T0_USR;
|
|
escr |= P4_ESCR_T1_USR;
|
|
}
|
|
hwc->config = p4_config_pack_escr(escr);
|
|
hwc->config |= p4_config_pack_cccr(cccr);
|
|
hwc->config |= P4_CONFIG_HT;
|
|
} else {
|
|
cccr &= ~P4_CCCR_OVF_PMI_T1;
|
|
cccr |= P4_CCCR_OVF_PMI_T0;
|
|
if (escr & P4_ESCR_T1_OS) {
|
|
escr &= ~P4_ESCR_T1_OS;
|
|
escr |= P4_ESCR_T0_OS;
|
|
}
|
|
if (escr & P4_ESCR_T1_USR) {
|
|
escr &= ~P4_ESCR_T1_USR;
|
|
escr |= P4_ESCR_T0_USR;
|
|
}
|
|
hwc->config = p4_config_pack_escr(escr);
|
|
hwc->config |= p4_config_pack_cccr(cccr);
|
|
hwc->config &= ~P4_CONFIG_HT;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* ESCR address hashing is tricky, ESCRs are not sequential
|
|
* in memory but all starts from MSR_P4_BSU_ESCR0 (0x03e0) and
|
|
* the metric between any ESCRs is laid in range [0xa0,0xe1]
|
|
*
|
|
* so we make ~70% filled hashtable
|
|
*/
|
|
|
|
#define P4_ESCR_MSR_BASE 0x000003a0
|
|
#define P4_ESCR_MSR_MAX 0x000003e1
|
|
#define P4_ESCR_MSR_TABLE_SIZE (P4_ESCR_MSR_MAX - P4_ESCR_MSR_BASE + 1)
|
|
#define P4_ESCR_MSR_IDX(msr) (msr - P4_ESCR_MSR_BASE)
|
|
#define P4_ESCR_MSR_TABLE_ENTRY(msr) [P4_ESCR_MSR_IDX(msr)] = msr
|
|
|
|
static const unsigned int p4_escr_table[P4_ESCR_MSR_TABLE_SIZE] = {
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ALF_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ALF_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BPU_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BPU_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BSU_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BSU_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR2),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR3),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR4),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR5),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_DAC_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_DAC_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FIRM_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FIRM_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FLAME_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FLAME_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FSB_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FSB_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IQ_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IQ_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IS_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IS_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ITLB_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ITLB_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IX_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IX_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MOB_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MOB_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MS_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MS_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_PMH_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_PMH_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_RAT_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_RAT_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SAAT_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SAAT_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SSU_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SSU_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TBPU_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TBPU_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TC_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TC_ESCR1),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_U2L_ESCR0),
|
|
P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_U2L_ESCR1),
|
|
};
|
|
|
|
static int p4_get_escr_idx(unsigned int addr)
|
|
{
|
|
unsigned int idx = P4_ESCR_MSR_IDX(addr);
|
|
|
|
if (unlikely(idx >= P4_ESCR_MSR_TABLE_SIZE ||
|
|
!p4_escr_table[idx])) {
|
|
WARN_ONCE(1, "P4 PMU: Wrong address passed: %x\n", addr);
|
|
return -1;
|
|
}
|
|
|
|
return idx;
|
|
}
|
|
|
|
static int p4_next_cntr(int thread, unsigned long *used_mask,
|
|
struct p4_event_bind *bind)
|
|
{
|
|
int i, j;
|
|
|
|
for (i = 0; i < P4_CNTR_LIMIT; i++) {
|
|
j = bind->cntr[thread][i];
|
|
if (j != -1 && !test_bit(j, used_mask))
|
|
return j;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
static int p4_pmu_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
|
|
{
|
|
unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
|
|
unsigned long escr_mask[BITS_TO_LONGS(P4_ESCR_MSR_TABLE_SIZE)];
|
|
int cpu = raw_smp_processor_id();
|
|
struct hw_perf_event *hwc;
|
|
struct p4_event_bind *bind;
|
|
unsigned int i, thread, num;
|
|
int cntr_idx, escr_idx;
|
|
|
|
bitmap_zero(used_mask, X86_PMC_IDX_MAX);
|
|
bitmap_zero(escr_mask, P4_ESCR_MSR_TABLE_SIZE);
|
|
|
|
for (i = 0, num = n; i < n; i++, num--) {
|
|
|
|
hwc = &cpuc->event_list[i]->hw;
|
|
thread = p4_ht_thread(cpu);
|
|
bind = p4_config_get_bind(hwc->config);
|
|
escr_idx = p4_get_escr_idx(bind->escr_msr[thread]);
|
|
if (unlikely(escr_idx == -1))
|
|
goto done;
|
|
|
|
if (hwc->idx != -1 && !p4_should_swap_ts(hwc->config, cpu)) {
|
|
cntr_idx = hwc->idx;
|
|
if (assign)
|
|
assign[i] = hwc->idx;
|
|
goto reserve;
|
|
}
|
|
|
|
cntr_idx = p4_next_cntr(thread, used_mask, bind);
|
|
if (cntr_idx == -1 || test_bit(escr_idx, escr_mask))
|
|
goto done;
|
|
|
|
p4_pmu_swap_config_ts(hwc, cpu);
|
|
if (assign)
|
|
assign[i] = cntr_idx;
|
|
reserve:
|
|
set_bit(cntr_idx, used_mask);
|
|
set_bit(escr_idx, escr_mask);
|
|
}
|
|
|
|
done:
|
|
return num ? -ENOSPC : 0;
|
|
}
|
|
|
|
static __initconst const struct x86_pmu p4_pmu = {
|
|
.name = "Netburst P4/Xeon",
|
|
.handle_irq = p4_pmu_handle_irq,
|
|
.disable_all = p4_pmu_disable_all,
|
|
.enable_all = p4_pmu_enable_all,
|
|
.enable = p4_pmu_enable_event,
|
|
.disable = p4_pmu_disable_event,
|
|
.eventsel = MSR_P4_BPU_CCCR0,
|
|
.perfctr = MSR_P4_BPU_PERFCTR0,
|
|
.event_map = p4_pmu_event_map,
|
|
.max_events = ARRAY_SIZE(p4_general_events),
|
|
.get_event_constraints = x86_get_event_constraints,
|
|
/*
|
|
* IF HT disabled we may need to use all
|
|
* ARCH_P4_MAX_CCCR counters simulaneously
|
|
* though leave it restricted at moment assuming
|
|
* HT is on
|
|
*/
|
|
.num_counters = ARCH_P4_MAX_CCCR,
|
|
.apic = 1,
|
|
.cntval_bits = 40,
|
|
.cntval_mask = (1ULL << 40) - 1,
|
|
.max_period = (1ULL << 39) - 1,
|
|
.hw_config = p4_hw_config,
|
|
.schedule_events = p4_pmu_schedule_events,
|
|
};
|
|
|
|
static __init int p4_pmu_init(void)
|
|
{
|
|
unsigned int low, high;
|
|
|
|
/* If we get stripped -- indexig fails */
|
|
BUILD_BUG_ON(ARCH_P4_MAX_CCCR > X86_PMC_MAX_GENERIC);
|
|
|
|
rdmsr(MSR_IA32_MISC_ENABLE, low, high);
|
|
if (!(low & (1 << 7))) {
|
|
pr_cont("unsupported Netburst CPU model %d ",
|
|
boot_cpu_data.x86_model);
|
|
return -ENODEV;
|
|
}
|
|
|
|
memcpy(hw_cache_event_ids, p4_hw_cache_event_ids,
|
|
sizeof(hw_cache_event_ids));
|
|
|
|
pr_cont("Netburst events, ");
|
|
|
|
x86_pmu = p4_pmu;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif /* CONFIG_CPU_SUP_INTEL */
|