665 lines
14 KiB
Plaintext
665 lines
14 KiB
Plaintext
/*
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* Device Tree Source for AM33xx clock data
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&scrm_clocks {
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sys_clkin_ck: sys_clkin_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
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ti,bit-shift = <22>;
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reg = <0x0040>;
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};
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adc_tsc_fck: adc_tsc_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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dcan0_fck: dcan0_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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dcan1_fck: dcan1_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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mcasp0_fck: mcasp0_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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mcasp1_fck: mcasp1_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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smartreflex0_fck: smartreflex0_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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smartreflex1_fck: smartreflex1_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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sha0_fck: sha0_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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aes0_fck: aes0_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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rng_fck: rng_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_clkin_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clocks = <&dpll_per_m2_ck>;
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ti,bit-shift = <0>;
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reg = <0x0664>;
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};
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ehrpwm0_tbclk: ehrpwm0_tbclk {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&ehrpwm0_gate_tbclk>;
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};
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ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clocks = <&dpll_per_m2_ck>;
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ti,bit-shift = <1>;
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reg = <0x0664>;
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};
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ehrpwm1_tbclk: ehrpwm1_tbclk {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&ehrpwm1_gate_tbclk>;
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};
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ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clocks = <&dpll_per_m2_ck>;
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ti,bit-shift = <2>;
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reg = <0x0664>;
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};
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ehrpwm2_tbclk: ehrpwm2_tbclk {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&ehrpwm2_gate_tbclk>;
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};
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};
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&prcm_clocks {
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clk_32768_ck: clk_32768_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk_rc32k_ck: clk_rc32k_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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virt_19200000_ck: virt_19200000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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};
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virt_24000000_ck: virt_24000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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virt_25000000_ck: virt_25000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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virt_26000000_ck: virt_26000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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};
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tclkin_ck: tclkin_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <12000000>;
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};
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dpll_core_ck: dpll_core_ck {
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#clock-cells = <0>;
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compatible = "ti,am3-dpll-core-clock";
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clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
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reg = <0x0490>, <0x045c>, <0x0468>;
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};
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dpll_core_x2_ck: dpll_core_x2_ck {
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#clock-cells = <0>;
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compatible = "ti,am3-dpll-x2-clock";
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clocks = <&dpll_core_ck>;
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};
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dpll_core_m4_ck: dpll_core_m4_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <31>;
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reg = <0x0480>;
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ti,index-starts-at-one;
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};
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dpll_core_m5_ck: dpll_core_m5_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <31>;
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reg = <0x0484>;
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ti,index-starts-at-one;
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};
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dpll_core_m6_ck: dpll_core_m6_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <31>;
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reg = <0x04d8>;
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ti,index-starts-at-one;
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};
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dpll_mpu_ck: dpll_mpu_ck {
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#clock-cells = <0>;
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compatible = "ti,am3-dpll-clock";
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clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
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reg = <0x0488>, <0x0420>, <0x042c>;
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};
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dpll_mpu_m2_ck: dpll_mpu_m2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_mpu_ck>;
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ti,max-div = <31>;
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reg = <0x04a8>;
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ti,index-starts-at-one;
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};
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dpll_ddr_ck: dpll_ddr_ck {
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#clock-cells = <0>;
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compatible = "ti,am3-dpll-no-gate-clock";
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clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
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reg = <0x0494>, <0x0434>, <0x0440>;
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};
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dpll_ddr_m2_ck: dpll_ddr_m2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_ddr_ck>;
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ti,max-div = <31>;
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reg = <0x04a0>;
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ti,index-starts-at-one;
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};
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dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_ddr_m2_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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dpll_disp_ck: dpll_disp_ck {
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#clock-cells = <0>;
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compatible = "ti,am3-dpll-no-gate-clock";
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clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
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reg = <0x0498>, <0x0448>, <0x0454>;
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};
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dpll_disp_m2_ck: dpll_disp_m2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_disp_ck>;
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ti,max-div = <31>;
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reg = <0x04a4>;
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ti,index-starts-at-one;
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ti,set-rate-parent;
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};
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dpll_per_ck: dpll_per_ck {
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#clock-cells = <0>;
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compatible = "ti,am3-dpll-no-gate-j-type-clock";
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clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
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reg = <0x048c>, <0x0470>, <0x049c>;
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};
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dpll_per_m2_ck: dpll_per_m2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_per_ck>;
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ti,max-div = <31>;
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reg = <0x04ac>;
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ti,index-starts-at-one;
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};
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dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_per_m2_ck>;
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clock-mult = <1>;
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clock-div = <4>;
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};
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dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_per_m2_ck>;
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clock-mult = <1>;
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clock-div = <4>;
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};
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cefuse_fck: cefuse_fck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sys_clkin_ck>;
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ti,bit-shift = <1>;
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reg = <0x0a20>;
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};
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clk_24mhz: clk_24mhz {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_per_m2_ck>;
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clock-mult = <1>;
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clock-div = <8>;
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};
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clkdiv32k_ck: clkdiv32k_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_24mhz>;
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clock-mult = <1>;
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clock-div = <732>;
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};
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clkdiv32k_ick: clkdiv32k_ick {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&clkdiv32k_ck>;
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ti,bit-shift = <1>;
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reg = <0x014c>;
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};
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l3_gclk: l3_gclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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pruss_ocp_gclk: pruss_ocp_gclk {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
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reg = <0x0530>;
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};
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mmu_fck: mmu_fck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_core_m4_ck>;
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ti,bit-shift = <1>;
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reg = <0x0914>;
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};
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timer1_fck: timer1_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
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reg = <0x0528>;
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};
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timer2_fck: timer2_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
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reg = <0x0508>;
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};
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timer3_fck: timer3_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
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reg = <0x050c>;
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};
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timer4_fck: timer4_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
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reg = <0x0510>;
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};
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timer5_fck: timer5_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
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reg = <0x0518>;
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};
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timer6_fck: timer6_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
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reg = <0x051c>;
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};
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timer7_fck: timer7_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
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reg = <0x0504>;
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};
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usbotg_fck: usbotg_fck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_per_ck>;
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ti,bit-shift = <8>;
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reg = <0x047c>;
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};
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dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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ieee5000_fck: ieee5000_fck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_core_m4_div2_ck>;
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ti,bit-shift = <1>;
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reg = <0x00e4>;
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};
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wdt1_fck: wdt1_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
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reg = <0x0538>;
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};
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l4_rtc_gclk: l4_rtc_gclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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l4hs_gclk: l4hs_gclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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l3s_gclk: l3s_gclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_div2_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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l4fw_gclk: l4fw_gclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_div2_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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l4ls_gclk: l4ls_gclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_div2_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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sysclk_div_ck: sysclk_div_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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cpsw_125mhz_gclk: cpsw_125mhz_gclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m5_ck>;
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|
clock-mult = <1>;
|
|
clock-div = <2>;
|
|
};
|
|
|
|
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
|
|
reg = <0x0520>;
|
|
};
|
|
|
|
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
|
|
reg = <0x053c>;
|
|
};
|
|
|
|
gpio0_dbclk: gpio0_dbclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&gpio0_dbclk_mux_ck>;
|
|
ti,bit-shift = <18>;
|
|
reg = <0x0408>;
|
|
};
|
|
|
|
gpio1_dbclk: gpio1_dbclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&clkdiv32k_ick>;
|
|
ti,bit-shift = <18>;
|
|
reg = <0x00ac>;
|
|
};
|
|
|
|
gpio2_dbclk: gpio2_dbclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&clkdiv32k_ick>;
|
|
ti,bit-shift = <18>;
|
|
reg = <0x00b0>;
|
|
};
|
|
|
|
gpio3_dbclk: gpio3_dbclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&clkdiv32k_ick>;
|
|
ti,bit-shift = <18>;
|
|
reg = <0x00b4>;
|
|
};
|
|
|
|
lcd_gclk: lcd_gclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
|
|
reg = <0x0534>;
|
|
ti,set-rate-parent;
|
|
};
|
|
|
|
mmc_clk: mmc_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&dpll_per_m2_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <2>;
|
|
};
|
|
|
|
gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x052c>;
|
|
};
|
|
|
|
gfx_fck_div_ck: gfx_fck_div_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&gfx_fclk_clksel_ck>;
|
|
reg = <0x052c>;
|
|
ti,max-div = <2>;
|
|
};
|
|
|
|
sysclkout_pre_ck: sysclkout_pre_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
|
|
reg = <0x0700>;
|
|
};
|
|
|
|
clkout2_div_ck: clkout2_div_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&sysclkout_pre_ck>;
|
|
ti,bit-shift = <3>;
|
|
ti,max-div = <8>;
|
|
reg = <0x0700>;
|
|
};
|
|
|
|
dbg_sysclk_ck: dbg_sysclk_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&sys_clkin_ck>;
|
|
ti,bit-shift = <19>;
|
|
reg = <0x0414>;
|
|
};
|
|
|
|
dbg_clka_ck: dbg_clka_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&dpll_core_m4_ck>;
|
|
ti,bit-shift = <30>;
|
|
reg = <0x0414>;
|
|
};
|
|
|
|
stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
|
|
ti,bit-shift = <22>;
|
|
reg = <0x0414>;
|
|
};
|
|
|
|
trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
|
|
ti,bit-shift = <20>;
|
|
reg = <0x0414>;
|
|
};
|
|
|
|
stm_clk_div_ck: stm_clk_div_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&stm_pmd_clock_mux_ck>;
|
|
ti,bit-shift = <27>;
|
|
ti,max-div = <64>;
|
|
reg = <0x0414>;
|
|
ti,index-power-of-two;
|
|
};
|
|
|
|
trace_clk_div_ck: trace_clk_div_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&trace_pmd_clk_mux_ck>;
|
|
ti,bit-shift = <24>;
|
|
ti,max-div = <64>;
|
|
reg = <0x0414>;
|
|
ti,index-power-of-two;
|
|
};
|
|
|
|
clkout2_ck: clkout2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&clkout2_div_ck>;
|
|
ti,bit-shift = <7>;
|
|
reg = <0x0700>;
|
|
};
|
|
};
|
|
|
|
&prcm_clockdomains {
|
|
clk_24mhz_clkdm: clk_24mhz_clkdm {
|
|
compatible = "ti,clockdomain";
|
|
clocks = <&clkdiv32k_ick>;
|
|
};
|
|
};
|