379 lines
10 KiB
C
379 lines
10 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SGI UV APIC functions (note: not an Intel compatible APIC)
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*
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* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/bootmem.h>
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#include <linux/module.h>
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#include <asm/smp.h>
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#include <asm/ipi.h>
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#include <asm/genapic.h>
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#include <asm/pgtable.h>
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#include <asm/uv/uv_mmrs.h>
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#include <asm/uv/uv_hub.h>
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DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
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EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
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struct uv_blade_info *uv_blade_info;
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EXPORT_SYMBOL_GPL(uv_blade_info);
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short *uv_node_to_blade;
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EXPORT_SYMBOL_GPL(uv_node_to_blade);
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short *uv_cpu_to_blade;
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EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
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short uv_possible_blades;
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EXPORT_SYMBOL_GPL(uv_possible_blades);
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/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
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static cpumask_t uv_target_cpus(void)
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{
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return cpumask_of_cpu(0);
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}
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static cpumask_t uv_vector_allocation_domain(int cpu)
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{
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cpumask_t domain = CPU_MASK_NONE;
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cpu_set(cpu, domain);
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return domain;
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}
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int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
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{
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unsigned long val;
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int pnode;
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pnode = uv_apicid_to_pnode(phys_apicid);
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val = (1UL << UVH_IPI_INT_SEND_SHFT) |
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(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
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(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
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APIC_DM_INIT;
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uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
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mdelay(10);
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val = (1UL << UVH_IPI_INT_SEND_SHFT) |
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(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
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(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
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APIC_DM_STARTUP;
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uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
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return 0;
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}
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static void uv_send_IPI_one(int cpu, int vector)
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{
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unsigned long val, apicid, lapicid;
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int pnode;
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apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
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lapicid = apicid & 0x3f; /* ZZZ macro needed */
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pnode = uv_apicid_to_pnode(apicid);
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val =
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(1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
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UVH_IPI_INT_APIC_ID_SHFT) |
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(vector << UVH_IPI_INT_VECTOR_SHFT);
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uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
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}
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static void uv_send_IPI_mask(cpumask_t mask, int vector)
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{
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unsigned int cpu;
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for (cpu = 0; cpu < NR_CPUS; ++cpu)
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if (cpu_isset(cpu, mask))
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uv_send_IPI_one(cpu, vector);
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}
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static void uv_send_IPI_allbutself(int vector)
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{
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cpumask_t mask = cpu_online_map;
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cpu_clear(smp_processor_id(), mask);
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if (!cpus_empty(mask))
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uv_send_IPI_mask(mask, vector);
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}
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static void uv_send_IPI_all(int vector)
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{
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uv_send_IPI_mask(cpu_online_map, vector);
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}
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static int uv_apic_id_registered(void)
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{
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return 1;
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}
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static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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cpu = first_cpu(cpumask);
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if ((unsigned)cpu < NR_CPUS)
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return per_cpu(x86_cpu_to_apicid, cpu);
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else
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return BAD_APICID;
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}
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static unsigned int phys_pkg_id(int index_msb)
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{
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return GET_APIC_ID(read_apic_id()) >> index_msb;
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}
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#ifdef ZZZ /* Needs x2apic patch */
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static void uv_send_IPI_self(int vector)
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{
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apic_write(APIC_SELF_IPI, vector);
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}
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#endif
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struct genapic apic_x2apic_uv_x = {
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.name = "UV large system",
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.int_delivery_mode = dest_Fixed,
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.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
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.target_cpus = uv_target_cpus,
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.vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
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.apic_id_registered = uv_apic_id_registered,
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.send_IPI_all = uv_send_IPI_all,
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.send_IPI_allbutself = uv_send_IPI_allbutself,
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.send_IPI_mask = uv_send_IPI_mask,
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/* ZZZ.send_IPI_self = uv_send_IPI_self, */
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.cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
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.phys_pkg_id = phys_pkg_id, /* Fixme ZZZ */
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};
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static __cpuinit void set_x2apic_extra_bits(int pnode)
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{
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__get_cpu_var(x2apic_extra_bits) = (pnode << 6);
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}
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/*
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* Called on boot cpu.
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*/
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static __init int boot_pnode_to_blade(int pnode)
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{
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int blade;
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for (blade = 0; blade < uv_num_possible_blades(); blade++)
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if (pnode == uv_blade_info[blade].pnode)
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return blade;
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BUG();
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}
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struct redir_addr {
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unsigned long redirect;
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unsigned long alias;
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};
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#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
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static __initdata struct redir_addr redir_addrs[] = {
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
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};
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static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
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{
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union uvh_si_alias0_overlay_config_u alias;
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union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
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int i;
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for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
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alias.v = uv_read_local_mmr(redir_addrs[i].alias);
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if (alias.s.base == 0) {
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*size = (1UL << alias.s.m_alias);
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redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
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*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
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return;
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}
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}
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BUG();
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}
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static __init void map_low_mmrs(void)
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{
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init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
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init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
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}
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enum map_type {map_wb, map_uc};
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static void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
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{
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unsigned long bytes, paddr;
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paddr = base << shift;
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bytes = (1UL << shift);
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printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
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paddr + bytes);
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if (map_type == map_uc)
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init_extra_mapping_uc(paddr, bytes);
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else
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init_extra_mapping_wb(paddr, bytes);
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}
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static __init void map_gru_high(int max_pnode)
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{
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union uvh_rh_gam_gru_overlay_config_mmr_u gru;
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int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
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gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
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if (gru.s.enable)
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map_high("GRU", gru.s.base, shift, map_wb);
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}
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static __init void map_config_high(int max_pnode)
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{
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union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
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int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
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cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
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if (cfg.s.enable)
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map_high("CONFIG", cfg.s.base, shift, map_uc);
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}
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static __init void map_mmr_high(int max_pnode)
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{
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union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
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int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
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mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
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if (mmr.s.enable)
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map_high("MMR", mmr.s.base, shift, map_uc);
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}
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static __init void map_mmioh_high(int max_pnode)
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{
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union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
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int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
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mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
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if (mmioh.s.enable)
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map_high("MMIOH", mmioh.s.base, shift, map_uc);
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}
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static __init void uv_system_init(void)
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{
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union uvh_si_addr_map_config_u m_n_config;
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union uvh_node_id_u node_id;
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unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
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int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
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int max_pnode = 0;
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unsigned long mmr_base, present;
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map_low_mmrs();
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m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
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m_val = m_n_config.s.m_skt;
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n_val = m_n_config.s.n_skt;
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mmr_base =
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uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
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~UV_MMR_ENABLE;
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printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
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for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
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uv_possible_blades +=
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hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
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printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
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bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
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uv_blade_info = alloc_bootmem_pages(bytes);
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get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
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bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
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uv_node_to_blade = alloc_bootmem_pages(bytes);
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memset(uv_node_to_blade, 255, bytes);
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bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
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uv_cpu_to_blade = alloc_bootmem_pages(bytes);
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memset(uv_cpu_to_blade, 255, bytes);
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blade = 0;
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for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
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present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
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for (j = 0; j < 64; j++) {
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if (!test_bit(j, &present))
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continue;
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uv_blade_info[blade].pnode = (i * 64 + j);
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uv_blade_info[blade].nr_possible_cpus = 0;
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uv_blade_info[blade].nr_online_cpus = 0;
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blade++;
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}
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}
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node_id.v = uv_read_local_mmr(UVH_NODE_ID);
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gnode_upper = (((unsigned long)node_id.s.node_id) &
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~((1 << n_val) - 1)) << m_val;
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for_each_present_cpu(cpu) {
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nid = cpu_to_node(cpu);
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pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
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blade = boot_pnode_to_blade(pnode);
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lcpu = uv_blade_info[blade].nr_possible_cpus;
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uv_blade_info[blade].nr_possible_cpus++;
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uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
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uv_cpu_hub_info(cpu)->lowmem_remap_top =
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lowmem_redir_base + lowmem_redir_size;
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uv_cpu_hub_info(cpu)->m_val = m_val;
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uv_cpu_hub_info(cpu)->n_val = m_val;
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uv_cpu_hub_info(cpu)->numa_blade_id = blade;
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uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
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uv_cpu_hub_info(cpu)->pnode = pnode;
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uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
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uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
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uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
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uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
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uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
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uv_node_to_blade[nid] = blade;
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uv_cpu_to_blade[cpu] = blade;
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max_pnode = max(pnode, max_pnode);
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printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
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"lcpu %d, blade %d\n",
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cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
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lcpu, blade);
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}
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map_gru_high(max_pnode);
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map_mmr_high(max_pnode);
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map_config_high(max_pnode);
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map_mmioh_high(max_pnode);
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}
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/*
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* Called on each cpu to initialize the per_cpu UV data area.
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* ZZZ hotplug not supported yet
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*/
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void __cpuinit uv_cpu_init(void)
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{
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if (!uv_node_to_blade)
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uv_system_init();
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uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
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if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
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set_x2apic_extra_bits(uv_hub_info->pnode);
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}
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