371 lines
10 KiB
C
371 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// JZ4740 CODEC driver
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//
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// Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/regmap.h>
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#include <linux/delay.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <sound/tlv.h>
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#define JZ4740_REG_CODEC_1 0x0
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#define JZ4740_REG_CODEC_2 0x4
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#define JZ4740_CODEC_1_LINE_ENABLE BIT(29)
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#define JZ4740_CODEC_1_MIC_ENABLE BIT(28)
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#define JZ4740_CODEC_1_SW1_ENABLE BIT(27)
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#define JZ4740_CODEC_1_ADC_ENABLE BIT(26)
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#define JZ4740_CODEC_1_SW2_ENABLE BIT(25)
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#define JZ4740_CODEC_1_DAC_ENABLE BIT(24)
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#define JZ4740_CODEC_1_VREF_DISABLE BIT(20)
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#define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19)
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#define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18)
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#define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17)
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#define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16)
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#define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14)
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#define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
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#define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12)
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#define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10))
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#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9)
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#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8)
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#define JZ4740_CODEC_1_SUSPEND BIT(1)
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#define JZ4740_CODEC_1_RESET BIT(0)
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#define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29
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#define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28
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#define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27
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#define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26
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#define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25
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#define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24
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#define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
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#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8
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#define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000
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#define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00
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#define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030
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#define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003
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#define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET 16
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#define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET 8
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#define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET 4
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#define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0
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static const struct reg_default jz4740_codec_reg_defaults[] = {
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{ JZ4740_REG_CODEC_1, 0x021b2302 },
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{ JZ4740_REG_CODEC_2, 0x00170803 },
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};
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struct jz4740_codec {
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struct regmap *regmap;
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};
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static const DECLARE_TLV_DB_RANGE(jz4740_mic_tlv,
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0, 2, TLV_DB_SCALE_ITEM(0, 600, 0),
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3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0)
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);
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static const DECLARE_TLV_DB_SCALE(jz4740_out_tlv, 0, 200, 0);
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static const DECLARE_TLV_DB_SCALE(jz4740_in_tlv, -3450, 150, 0);
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static const struct snd_kcontrol_new jz4740_codec_controls[] = {
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SOC_SINGLE_TLV("Master Playback Volume", JZ4740_REG_CODEC_2,
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JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0,
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jz4740_out_tlv),
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SOC_SINGLE_TLV("Master Capture Volume", JZ4740_REG_CODEC_2,
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JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0,
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jz4740_in_tlv),
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SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1,
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JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
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SOC_SINGLE_TLV("Mic Capture Volume", JZ4740_REG_CODEC_2,
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JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0,
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jz4740_mic_tlv),
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};
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static const struct snd_kcontrol_new jz4740_codec_output_controls[] = {
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SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1,
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JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
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SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1,
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JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
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};
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static const struct snd_kcontrol_new jz4740_codec_input_controls[] = {
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SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1,
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JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
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SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1,
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JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
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};
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static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = {
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SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1,
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JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0),
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SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1,
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JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0),
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SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1,
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JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1,
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jz4740_codec_output_controls,
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ARRAY_SIZE(jz4740_codec_output_controls)),
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SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
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jz4740_codec_input_controls,
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ARRAY_SIZE(jz4740_codec_input_controls)),
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SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
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SND_SOC_DAPM_OUTPUT("LOUT"),
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SND_SOC_DAPM_OUTPUT("ROUT"),
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SND_SOC_DAPM_INPUT("MIC"),
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SND_SOC_DAPM_INPUT("LIN"),
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SND_SOC_DAPM_INPUT("RIN"),
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};
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static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = {
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{"Line Input", NULL, "LIN"},
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{"Line Input", NULL, "RIN"},
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{"Input Mixer", "Line Capture Switch", "Line Input"},
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{"Input Mixer", "Mic Capture Switch", "MIC"},
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{"ADC", NULL, "Input Mixer"},
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{"Output Mixer", "Bypass Switch", "Input Mixer"},
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{"Output Mixer", "DAC Switch", "DAC"},
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{"LOUT", NULL, "Output Mixer"},
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{"ROUT", NULL, "Output Mixer"},
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};
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static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
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{
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struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(dai->component);
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uint32_t val;
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switch (params_rate(params)) {
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case 8000:
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val = 0;
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break;
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case 11025:
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val = 1;
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break;
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case 12000:
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val = 2;
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break;
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case 16000:
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val = 3;
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break;
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case 22050:
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val = 4;
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break;
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case 24000:
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val = 5;
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break;
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case 32000:
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val = 6;
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break;
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case 44100:
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val = 7;
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break;
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case 48000:
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val = 8;
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break;
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default:
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return -EINVAL;
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}
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val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET;
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regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_2,
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JZ4740_CODEC_2_SAMPLE_RATE_MASK, val);
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return 0;
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}
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static const struct snd_soc_dai_ops jz4740_codec_dai_ops = {
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.hw_params = jz4740_codec_hw_params,
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};
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static struct snd_soc_dai_driver jz4740_codec_dai = {
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.name = "jz4740-hifi",
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.playback = {
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.stream_name = "Playback",
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
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},
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.capture = {
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.stream_name = "Capture",
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
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},
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.ops = &jz4740_codec_dai_ops,
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.symmetric_rates = 1,
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};
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static void jz4740_codec_wakeup(struct regmap *regmap)
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{
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regmap_update_bits(regmap, JZ4740_REG_CODEC_1,
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JZ4740_CODEC_1_RESET, JZ4740_CODEC_1_RESET);
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udelay(2);
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regmap_update_bits(regmap, JZ4740_REG_CODEC_1,
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JZ4740_CODEC_1_SUSPEND | JZ4740_CODEC_1_RESET, 0);
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regcache_sync(regmap);
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}
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static int jz4740_codec_set_bias_level(struct snd_soc_component *component,
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enum snd_soc_bias_level level)
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{
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struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(component);
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struct regmap *regmap = jz4740_codec->regmap;
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unsigned int mask;
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unsigned int value;
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switch (level) {
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case SND_SOC_BIAS_ON:
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break;
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case SND_SOC_BIAS_PREPARE:
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mask = JZ4740_CODEC_1_VREF_DISABLE |
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JZ4740_CODEC_1_VREF_AMP_DISABLE |
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JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
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value = 0;
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regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
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break;
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case SND_SOC_BIAS_STANDBY:
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/* The only way to clear the suspend flag is to reset the codec */
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if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
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jz4740_codec_wakeup(regmap);
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mask = JZ4740_CODEC_1_VREF_DISABLE |
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JZ4740_CODEC_1_VREF_AMP_DISABLE |
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JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
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value = JZ4740_CODEC_1_VREF_DISABLE |
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JZ4740_CODEC_1_VREF_AMP_DISABLE |
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JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
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regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
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break;
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case SND_SOC_BIAS_OFF:
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mask = JZ4740_CODEC_1_SUSPEND;
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value = JZ4740_CODEC_1_SUSPEND;
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regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
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regcache_mark_dirty(regmap);
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break;
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default:
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break;
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}
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return 0;
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}
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static int jz4740_codec_dev_probe(struct snd_soc_component *component)
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{
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struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(component);
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regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_1,
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JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
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return 0;
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}
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static const struct snd_soc_component_driver soc_codec_dev_jz4740_codec = {
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.probe = jz4740_codec_dev_probe,
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.set_bias_level = jz4740_codec_set_bias_level,
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.controls = jz4740_codec_controls,
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.num_controls = ARRAY_SIZE(jz4740_codec_controls),
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.dapm_widgets = jz4740_codec_dapm_widgets,
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.num_dapm_widgets = ARRAY_SIZE(jz4740_codec_dapm_widgets),
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.dapm_routes = jz4740_codec_dapm_routes,
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.num_dapm_routes = ARRAY_SIZE(jz4740_codec_dapm_routes),
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.suspend_bias_off = 1,
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.idle_bias_on = 1,
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.use_pmdown_time = 1,
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.endianness = 1,
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.non_legacy_dai_naming = 1,
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};
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static const struct regmap_config jz4740_codec_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = JZ4740_REG_CODEC_2,
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.reg_defaults = jz4740_codec_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(jz4740_codec_reg_defaults),
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.cache_type = REGCACHE_RBTREE,
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};
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static int jz4740_codec_probe(struct platform_device *pdev)
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{
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int ret;
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struct jz4740_codec *jz4740_codec;
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struct resource *mem;
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void __iomem *base;
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jz4740_codec = devm_kzalloc(&pdev->dev, sizeof(*jz4740_codec),
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GFP_KERNEL);
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if (!jz4740_codec)
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return -ENOMEM;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(base))
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return PTR_ERR(base);
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jz4740_codec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
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&jz4740_codec_regmap_config);
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if (IS_ERR(jz4740_codec->regmap))
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return PTR_ERR(jz4740_codec->regmap);
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platform_set_drvdata(pdev, jz4740_codec);
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ret = devm_snd_soc_register_component(&pdev->dev,
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&soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1);
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if (ret)
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dev_err(&pdev->dev, "Failed to register codec\n");
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return ret;
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}
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#ifdef CONFIG_OF
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static const struct of_device_id jz4740_codec_of_matches[] = {
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{ .compatible = "ingenic,jz4740-codec", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, jz4740_codec_of_matches);
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#endif
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static struct platform_driver jz4740_codec_driver = {
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.probe = jz4740_codec_probe,
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.driver = {
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.name = "jz4740-codec",
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.of_match_table = of_match_ptr(jz4740_codec_of_matches),
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},
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};
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module_platform_driver(jz4740_codec_driver);
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MODULE_DESCRIPTION("JZ4740 SoC internal codec driver");
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MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:jz4740-codec");
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