488 lines
12 KiB
C
488 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Intel IXP4xx Queue Manager driver for Linux
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*
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* Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
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*/
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/soc/ixp4xx/qmgr.h>
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#include <linux/soc/ixp4xx/cpu.h>
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static struct qmgr_regs __iomem *qmgr_regs;
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static int qmgr_irq_1;
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static int qmgr_irq_2;
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static spinlock_t qmgr_lock;
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static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
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static void (*irq_handlers[QUEUES])(void *pdev);
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static void *irq_pdevs[QUEUES];
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#if DEBUG_QMGR
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char qmgr_queue_descs[QUEUES][32];
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#endif
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void qmgr_put_entry(unsigned int queue, u32 val)
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{
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#if DEBUG_QMGR
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BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
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printk(KERN_DEBUG "Queue %s(%i) put %X\n",
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qmgr_queue_descs[queue], queue, val);
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#endif
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__raw_writel(val, &qmgr_regs->acc[queue][0]);
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}
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u32 qmgr_get_entry(unsigned int queue)
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{
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u32 val;
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val = __raw_readl(&qmgr_regs->acc[queue][0]);
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#if DEBUG_QMGR
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BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
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printk(KERN_DEBUG "Queue %s(%i) get %X\n",
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qmgr_queue_descs[queue], queue, val);
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#endif
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return val;
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}
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static int __qmgr_get_stat1(unsigned int queue)
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{
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return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
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>> ((queue & 7) << 2)) & 0xF;
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}
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static int __qmgr_get_stat2(unsigned int queue)
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{
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BUG_ON(queue >= HALF_QUEUES);
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return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
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>> ((queue & 0xF) << 1)) & 0x3;
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}
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/**
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* qmgr_stat_empty() - checks if a hardware queue is empty
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* @queue: queue number
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*
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* Returns non-zero value if the queue is empty.
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*/
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int qmgr_stat_empty(unsigned int queue)
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{
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BUG_ON(queue >= HALF_QUEUES);
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return __qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY;
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}
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/**
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* qmgr_stat_below_low_watermark() - checks if a queue is below low watermark
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* @queue: queue number
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*
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* Returns non-zero value if the queue is below low watermark.
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*/
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int qmgr_stat_below_low_watermark(unsigned int queue)
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{
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if (queue >= HALF_QUEUES)
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return (__raw_readl(&qmgr_regs->statne_h) >>
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(queue - HALF_QUEUES)) & 0x01;
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return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY;
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}
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/**
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* qmgr_stat_full() - checks if a hardware queue is full
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* @queue: queue number
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*
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* Returns non-zero value if the queue is full.
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*/
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int qmgr_stat_full(unsigned int queue)
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{
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if (queue >= HALF_QUEUES)
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return (__raw_readl(&qmgr_regs->statf_h) >>
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(queue - HALF_QUEUES)) & 0x01;
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return __qmgr_get_stat1(queue) & QUEUE_STAT1_FULL;
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}
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/**
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* qmgr_stat_overflow() - checks if a hardware queue experienced overflow
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* @queue: queue number
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*
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* Returns non-zero value if the queue experienced overflow.
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*/
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int qmgr_stat_overflow(unsigned int queue)
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{
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return __qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW;
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}
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void qmgr_set_irq(unsigned int queue, int src,
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void (*handler)(void *pdev), void *pdev)
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{
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unsigned long flags;
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spin_lock_irqsave(&qmgr_lock, flags);
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if (queue < HALF_QUEUES) {
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u32 __iomem *reg;
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int bit;
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BUG_ON(src > QUEUE_IRQ_SRC_NOT_FULL);
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reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */
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bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
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__raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit),
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reg);
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} else
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/* IRQ source for queues 32-63 is fixed */
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BUG_ON(src != QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY);
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irq_handlers[queue] = handler;
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irq_pdevs[queue] = pdev;
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spin_unlock_irqrestore(&qmgr_lock, flags);
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}
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static irqreturn_t qmgr_irq1_a0(int irq, void *pdev)
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{
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int i, ret = 0;
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u32 en_bitmap, src, stat;
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/* ACK - it may clear any bits so don't rely on it */
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__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]);
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en_bitmap = __raw_readl(&qmgr_regs->irqen[0]);
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while (en_bitmap) {
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i = __fls(en_bitmap); /* number of the last "low" queue */
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en_bitmap &= ~BIT(i);
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src = __raw_readl(&qmgr_regs->irqsrc[i >> 3]);
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stat = __raw_readl(&qmgr_regs->stat1[i >> 3]);
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if (src & 4) /* the IRQ condition is inverted */
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stat = ~stat;
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if (stat & BIT(src & 3)) {
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irq_handlers[i](irq_pdevs[i]);
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ret = IRQ_HANDLED;
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}
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}
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return ret;
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}
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static irqreturn_t qmgr_irq2_a0(int irq, void *pdev)
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{
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int i, ret = 0;
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u32 req_bitmap;
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/* ACK - it may clear any bits so don't rely on it */
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__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[1]);
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req_bitmap = __raw_readl(&qmgr_regs->irqen[1]) &
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__raw_readl(&qmgr_regs->statne_h);
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while (req_bitmap) {
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i = __fls(req_bitmap); /* number of the last "high" queue */
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req_bitmap &= ~BIT(i);
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irq_handlers[HALF_QUEUES + i](irq_pdevs[HALF_QUEUES + i]);
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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static irqreturn_t qmgr_irq(int irq, void *pdev)
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{
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int i, half = (irq == qmgr_irq_1 ? 0 : 1);
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u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[half]);
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if (!req_bitmap)
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return 0;
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__raw_writel(req_bitmap, &qmgr_regs->irqstat[half]); /* ACK */
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while (req_bitmap) {
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i = __fls(req_bitmap); /* number of the last queue */
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req_bitmap &= ~BIT(i);
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i += half * HALF_QUEUES;
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irq_handlers[i](irq_pdevs[i]);
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}
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return IRQ_HANDLED;
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}
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void qmgr_enable_irq(unsigned int queue)
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{
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unsigned long flags;
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int half = queue / 32;
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u32 mask = 1 << (queue & (HALF_QUEUES - 1));
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spin_lock_irqsave(&qmgr_lock, flags);
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__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask,
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&qmgr_regs->irqen[half]);
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spin_unlock_irqrestore(&qmgr_lock, flags);
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}
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void qmgr_disable_irq(unsigned int queue)
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{
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unsigned long flags;
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int half = queue / 32;
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u32 mask = 1 << (queue & (HALF_QUEUES - 1));
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spin_lock_irqsave(&qmgr_lock, flags);
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__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask,
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&qmgr_regs->irqen[half]);
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__raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */
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spin_unlock_irqrestore(&qmgr_lock, flags);
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}
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static inline void shift_mask(u32 *mask)
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{
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mask[3] = mask[3] << 1 | mask[2] >> 31;
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mask[2] = mask[2] << 1 | mask[1] >> 31;
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mask[1] = mask[1] << 1 | mask[0] >> 31;
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mask[0] <<= 1;
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}
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#if DEBUG_QMGR
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int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
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unsigned int nearly_empty_watermark,
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unsigned int nearly_full_watermark,
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const char *desc_format, const char* name)
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#else
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int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
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unsigned int nearly_empty_watermark,
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unsigned int nearly_full_watermark)
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#endif
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{
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u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
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int err;
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BUG_ON(queue >= QUEUES);
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if ((nearly_empty_watermark | nearly_full_watermark) & ~7)
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return -EINVAL;
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switch (len) {
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case 16:
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cfg = 0 << 24;
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mask[0] = 0x1;
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break;
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case 32:
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cfg = 1 << 24;
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mask[0] = 0x3;
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break;
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case 64:
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cfg = 2 << 24;
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mask[0] = 0xF;
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break;
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case 128:
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cfg = 3 << 24;
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mask[0] = 0xFF;
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break;
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default:
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return -EINVAL;
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}
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cfg |= nearly_empty_watermark << 26;
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cfg |= nearly_full_watermark << 29;
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len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */
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mask[1] = mask[2] = mask[3] = 0;
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if (!try_module_get(THIS_MODULE))
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return -ENODEV;
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spin_lock_irq(&qmgr_lock);
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if (__raw_readl(&qmgr_regs->sram[queue])) {
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err = -EBUSY;
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goto err;
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}
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while (1) {
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if (!(used_sram_bitmap[0] & mask[0]) &&
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!(used_sram_bitmap[1] & mask[1]) &&
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!(used_sram_bitmap[2] & mask[2]) &&
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!(used_sram_bitmap[3] & mask[3]))
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break; /* found free space */
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addr++;
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shift_mask(mask);
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if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {
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printk(KERN_ERR "qmgr: no free SRAM space for"
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" queue %i\n", queue);
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err = -ENOMEM;
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goto err;
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}
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}
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used_sram_bitmap[0] |= mask[0];
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used_sram_bitmap[1] |= mask[1];
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used_sram_bitmap[2] |= mask[2];
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used_sram_bitmap[3] |= mask[3];
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__raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
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#if DEBUG_QMGR
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snprintf(qmgr_queue_descs[queue], sizeof(qmgr_queue_descs[0]),
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desc_format, name);
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printk(KERN_DEBUG "qmgr: requested queue %s(%i) addr = 0x%02X\n",
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qmgr_queue_descs[queue], queue, addr);
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#endif
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spin_unlock_irq(&qmgr_lock);
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return 0;
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err:
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spin_unlock_irq(&qmgr_lock);
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module_put(THIS_MODULE);
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return err;
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}
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void qmgr_release_queue(unsigned int queue)
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{
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u32 cfg, addr, mask[4];
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BUG_ON(queue >= QUEUES); /* not in valid range */
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spin_lock_irq(&qmgr_lock);
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cfg = __raw_readl(&qmgr_regs->sram[queue]);
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addr = (cfg >> 14) & 0xFF;
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BUG_ON(!addr); /* not requested */
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switch ((cfg >> 24) & 3) {
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case 0: mask[0] = 0x1; break;
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case 1: mask[0] = 0x3; break;
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case 2: mask[0] = 0xF; break;
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case 3: mask[0] = 0xFF; break;
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}
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mask[1] = mask[2] = mask[3] = 0;
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while (addr--)
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shift_mask(mask);
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#if DEBUG_QMGR
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printk(KERN_DEBUG "qmgr: releasing queue %s(%i)\n",
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qmgr_queue_descs[queue], queue);
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qmgr_queue_descs[queue][0] = '\x0';
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#endif
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while ((addr = qmgr_get_entry(queue)))
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printk(KERN_ERR "qmgr: released queue %i not empty: 0x%08X\n",
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queue, addr);
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__raw_writel(0, &qmgr_regs->sram[queue]);
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used_sram_bitmap[0] &= ~mask[0];
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used_sram_bitmap[1] &= ~mask[1];
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used_sram_bitmap[2] &= ~mask[2];
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used_sram_bitmap[3] &= ~mask[3];
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irq_handlers[queue] = NULL; /* catch IRQ bugs */
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spin_unlock_irq(&qmgr_lock);
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module_put(THIS_MODULE);
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}
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static int ixp4xx_qmgr_probe(struct platform_device *pdev)
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{
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int i, err;
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irq_handler_t handler1, handler2;
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struct device *dev = &pdev->dev;
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struct resource *res;
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int irq1, irq2;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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qmgr_regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(qmgr_regs))
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return PTR_ERR(qmgr_regs);
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irq1 = platform_get_irq(pdev, 0);
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if (irq1 <= 0)
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return irq1 ? irq1 : -EINVAL;
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qmgr_irq_1 = irq1;
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irq2 = platform_get_irq(pdev, 1);
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if (irq2 <= 0)
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return irq2 ? irq2 : -EINVAL;
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qmgr_irq_2 = irq2;
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/* reset qmgr registers */
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for (i = 0; i < 4; i++) {
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__raw_writel(0x33333333, &qmgr_regs->stat1[i]);
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__raw_writel(0, &qmgr_regs->irqsrc[i]);
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}
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for (i = 0; i < 2; i++) {
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__raw_writel(0, &qmgr_regs->stat2[i]);
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__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
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__raw_writel(0, &qmgr_regs->irqen[i]);
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}
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__raw_writel(0xFFFFFFFF, &qmgr_regs->statne_h);
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__raw_writel(0, &qmgr_regs->statf_h);
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for (i = 0; i < QUEUES; i++)
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__raw_writel(0, &qmgr_regs->sram[i]);
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if (cpu_is_ixp42x_rev_a0()) {
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handler1 = qmgr_irq1_a0;
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handler2 = qmgr_irq2_a0;
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} else
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handler1 = handler2 = qmgr_irq;
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err = devm_request_irq(dev, irq1, handler1, 0, "IXP4xx Queue Manager",
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NULL);
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if (err) {
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dev_err(dev, "failed to request IRQ%i (%i)\n",
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irq1, err);
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return err;
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}
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err = devm_request_irq(dev, irq2, handler2, 0, "IXP4xx Queue Manager",
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NULL);
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if (err) {
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dev_err(dev, "failed to request IRQ%i (%i)\n",
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irq2, err);
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return err;
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}
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used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
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spin_lock_init(&qmgr_lock);
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dev_info(dev, "IXP4xx Queue Manager initialized.\n");
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return 0;
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}
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static int ixp4xx_qmgr_remove(struct platform_device *pdev)
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{
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synchronize_irq(qmgr_irq_1);
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synchronize_irq(qmgr_irq_2);
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return 0;
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}
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static const struct of_device_id ixp4xx_qmgr_of_match[] = {
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{
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.compatible = "intel,ixp4xx-ahb-queue-manager",
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},
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{},
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};
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static struct platform_driver ixp4xx_qmgr_driver = {
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.driver = {
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.name = "ixp4xx-qmgr",
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.of_match_table = ixp4xx_qmgr_of_match,
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},
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.probe = ixp4xx_qmgr_probe,
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.remove = ixp4xx_qmgr_remove,
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};
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module_platform_driver(ixp4xx_qmgr_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Krzysztof Halasa");
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EXPORT_SYMBOL(qmgr_put_entry);
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EXPORT_SYMBOL(qmgr_get_entry);
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EXPORT_SYMBOL(qmgr_stat_empty);
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EXPORT_SYMBOL(qmgr_stat_below_low_watermark);
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EXPORT_SYMBOL(qmgr_stat_full);
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EXPORT_SYMBOL(qmgr_stat_overflow);
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EXPORT_SYMBOL(qmgr_set_irq);
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EXPORT_SYMBOL(qmgr_enable_irq);
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EXPORT_SYMBOL(qmgr_disable_irq);
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#if DEBUG_QMGR
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EXPORT_SYMBOL(qmgr_queue_descs);
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EXPORT_SYMBOL(qmgr_request_queue);
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#else
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EXPORT_SYMBOL(__qmgr_request_queue);
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#endif
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EXPORT_SYMBOL(qmgr_release_queue);
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