307 lines
8.3 KiB
C
307 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Driver for Microchip 10BASE-T1S PHYs
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*
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* Support: Microchip Phys:
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* lan8670/1/2 Rev.B1
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* lan8650/1 Rev.B0 Internal PHYs
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#define PHY_ID_LAN867X_REVB1 0x0007C162
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#define PHY_ID_LAN865X_REVB0 0x0007C1B3
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#define LAN867X_REG_STS2 0x0019
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#define LAN867x_RESET_COMPLETE_STS BIT(11)
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#define LAN865X_REG_CFGPARAM_ADDR 0x00D8
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#define LAN865X_REG_CFGPARAM_DATA 0x00D9
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#define LAN865X_REG_CFGPARAM_CTRL 0x00DA
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#define LAN865X_REG_STS2 0x0019
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#define LAN865X_CFGPARAM_READ_ENABLE BIT(1)
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/* The arrays below are pulled from the following table from AN1699
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* Access MMD Address Value Mask
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* RMW 0x1F 0x00D0 0x0002 0x0E03
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* RMW 0x1F 0x00D1 0x0000 0x0300
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* RMW 0x1F 0x0084 0x3380 0xFFC0
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* RMW 0x1F 0x0085 0x0006 0x000F
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* RMW 0x1F 0x008A 0xC000 0xF800
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* RMW 0x1F 0x0087 0x801C 0x801C
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* RMW 0x1F 0x0088 0x033F 0x1FFF
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* W 0x1F 0x008B 0x0404 ------
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* RMW 0x1F 0x0080 0x0600 0x0600
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* RMW 0x1F 0x00F1 0x2400 0x7F00
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* RMW 0x1F 0x0096 0x2000 0x2000
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* W 0x1F 0x0099 0x7F80 ------
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*/
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static const u32 lan867x_revb1_fixup_registers[12] = {
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0x00D0, 0x00D1, 0x0084, 0x0085,
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0x008A, 0x0087, 0x0088, 0x008B,
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0x0080, 0x00F1, 0x0096, 0x0099,
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};
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static const u16 lan867x_revb1_fixup_values[12] = {
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0x0002, 0x0000, 0x3380, 0x0006,
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0xC000, 0x801C, 0x033F, 0x0404,
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0x0600, 0x2400, 0x2000, 0x7F80,
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};
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static const u16 lan867x_revb1_fixup_masks[12] = {
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0x0E03, 0x0300, 0xFFC0, 0x000F,
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0xF800, 0x801C, 0x1FFF, 0xFFFF,
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0x0600, 0x7F00, 0x2000, 0xFFFF,
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};
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/* LAN865x Rev.B0 configuration parameters from AN1760 */
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static const u32 lan865x_revb0_fixup_registers[28] = {
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0x0091, 0x0081, 0x0043, 0x0044,
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0x0045, 0x0053, 0x0054, 0x0055,
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0x0040, 0x0050, 0x00D0, 0x00E9,
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0x00F5, 0x00F4, 0x00F8, 0x00F9,
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0x00B0, 0x00B1, 0x00B2, 0x00B3,
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0x00B4, 0x00B5, 0x00B6, 0x00B7,
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0x00B8, 0x00B9, 0x00BA, 0x00BB,
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};
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static const u16 lan865x_revb0_fixup_values[28] = {
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0x9660, 0x00C0, 0x00FF, 0xFFFF,
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0x0000, 0x00FF, 0xFFFF, 0x0000,
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0x0002, 0x0002, 0x5F21, 0x9E50,
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0x1CF8, 0xC020, 0x9B00, 0x4E53,
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0x0103, 0x0910, 0x1D26, 0x002A,
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0x0103, 0x070D, 0x1720, 0x0027,
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0x0509, 0x0E13, 0x1C25, 0x002B,
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};
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static const u16 lan865x_revb0_fixup_cfg_regs[5] = {
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0x0084, 0x008A, 0x00AD, 0x00AE, 0x00AF
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};
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/* Pulled from AN1760 describing 'indirect read'
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*
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* write_register(0x4, 0x00D8, addr)
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* write_register(0x4, 0x00DA, 0x2)
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* return (int8)(read_register(0x4, 0x00D9))
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*
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* 0x4 refers to memory map selector 4, which maps to MDIO_MMD_VEND2
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*/
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static int lan865x_revb0_indirect_read(struct phy_device *phydev, u16 addr)
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{
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int ret;
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_ADDR,
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addr);
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if (ret)
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return ret;
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_CTRL,
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LAN865X_CFGPARAM_READ_ENABLE);
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if (ret)
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return ret;
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return phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_DATA);
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}
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/* This is pulled straight from AN1760 from 'calculation of offset 1' &
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* 'calculation of offset 2'
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*/
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static int lan865x_generate_cfg_offsets(struct phy_device *phydev, s8 offsets[2])
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{
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const u16 fixup_regs[2] = {0x0004, 0x0008};
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int ret;
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for (int i = 0; i < ARRAY_SIZE(fixup_regs); i++) {
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ret = lan865x_revb0_indirect_read(phydev, fixup_regs[i]);
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if (ret < 0)
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return ret;
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if (ret & BIT(4))
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offsets[i] = ret | 0xE0;
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else
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offsets[i] = ret;
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}
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return 0;
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}
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static int lan865x_read_cfg_params(struct phy_device *phydev, u16 cfg_params[])
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{
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int ret;
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for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs); i++) {
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
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lan865x_revb0_fixup_cfg_regs[i]);
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if (ret < 0)
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return ret;
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cfg_params[i] = (u16)ret;
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}
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return 0;
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}
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static int lan865x_write_cfg_params(struct phy_device *phydev, u16 cfg_params[])
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{
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int ret;
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for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs); i++) {
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
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lan865x_revb0_fixup_cfg_regs[i],
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cfg_params[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int lan865x_setup_cfgparam(struct phy_device *phydev)
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{
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u16 cfg_params[ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs)];
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u16 cfg_results[5];
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s8 offsets[2];
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int ret;
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ret = lan865x_generate_cfg_offsets(phydev, offsets);
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if (ret)
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return ret;
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ret = lan865x_read_cfg_params(phydev, cfg_params);
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if (ret)
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return ret;
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cfg_results[0] = (cfg_params[0] & 0x000F) |
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FIELD_PREP(GENMASK(15, 10), 9 + offsets[0]) |
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FIELD_PREP(GENMASK(15, 4), 14 + offsets[0]);
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cfg_results[1] = (cfg_params[1] & 0x03FF) |
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FIELD_PREP(GENMASK(15, 10), 40 + offsets[1]);
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cfg_results[2] = (cfg_params[2] & 0xC0C0) |
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FIELD_PREP(GENMASK(15, 8), 5 + offsets[0]) |
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(9 + offsets[0]);
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cfg_results[3] = (cfg_params[3] & 0xC0C0) |
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FIELD_PREP(GENMASK(15, 8), 9 + offsets[0]) |
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(14 + offsets[0]);
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cfg_results[4] = (cfg_params[4] & 0xC0C0) |
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FIELD_PREP(GENMASK(15, 8), 17 + offsets[0]) |
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(22 + offsets[0]);
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return lan865x_write_cfg_params(phydev, cfg_results);
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}
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static int lan865x_revb0_config_init(struct phy_device *phydev)
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{
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int ret;
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/* Reference to AN1760
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* https://ww1.microchip.com/downloads/aemDocuments/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8650-1-Configuration-60001760.pdf
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*/
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for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_registers); i++) {
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
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lan865x_revb0_fixup_registers[i],
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lan865x_revb0_fixup_values[i]);
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if (ret)
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return ret;
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}
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/* Function to calculate and write the configuration parameters in the
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* 0x0084, 0x008A, 0x00AD, 0x00AE and 0x00AF registers (from AN1760)
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*/
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return lan865x_setup_cfgparam(phydev);
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}
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static int lan867x_revb1_config_init(struct phy_device *phydev)
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{
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int err;
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/* The chip completes a reset in 3us, we might get here earlier than
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* that, as an added margin we'll conditionally sleep 5us.
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*/
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err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2);
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if (err < 0)
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return err;
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if (!(err & LAN867x_RESET_COMPLETE_STS)) {
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udelay(5);
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err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2);
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if (err < 0)
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return err;
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if (!(err & LAN867x_RESET_COMPLETE_STS)) {
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phydev_err(phydev, "PHY reset failed\n");
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return -ENODEV;
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}
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}
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/* Reference to AN1699
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* https://ww1.microchip.com/downloads/aemDocuments/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8670-1-2-config-60001699.pdf
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* AN1699 says Read, Modify, Write, but the Write is not required if the
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* register already has the required value. So it is safe to use
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* phy_modify_mmd here.
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*/
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for (int i = 0; i < ARRAY_SIZE(lan867x_revb1_fixup_registers); i++) {
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err = phy_modify_mmd(phydev, MDIO_MMD_VEND2,
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lan867x_revb1_fixup_registers[i],
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lan867x_revb1_fixup_masks[i],
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lan867x_revb1_fixup_values[i]);
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if (err)
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return err;
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}
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return 0;
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}
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static int lan86xx_read_status(struct phy_device *phydev)
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{
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/* The phy has some limitations, namely:
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* - always reports link up
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* - only supports 10MBit half duplex
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* - does not support auto negotiate
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*/
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phydev->link = 1;
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phydev->duplex = DUPLEX_HALF;
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phydev->speed = SPEED_10;
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phydev->autoneg = AUTONEG_DISABLE;
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return 0;
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}
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static struct phy_driver microchip_t1s_driver[] = {
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{
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PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1),
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.name = "LAN867X Rev.B1",
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.features = PHY_BASIC_T1S_P2MP_FEATURES,
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.config_init = lan867x_revb1_config_init,
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.read_status = lan86xx_read_status,
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.get_plca_cfg = genphy_c45_plca_get_cfg,
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.set_plca_cfg = genphy_c45_plca_set_cfg,
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.get_plca_status = genphy_c45_plca_get_status,
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},
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{
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PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB0),
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.name = "LAN865X Rev.B0 Internal Phy",
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.features = PHY_BASIC_T1S_P2MP_FEATURES,
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.config_init = lan865x_revb0_config_init,
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.read_status = lan86xx_read_status,
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.get_plca_cfg = genphy_c45_plca_get_cfg,
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.set_plca_cfg = genphy_c45_plca_set_cfg,
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.get_plca_status = genphy_c45_plca_get_status,
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},
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};
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module_phy_driver(microchip_t1s_driver);
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static struct mdio_device_id __maybe_unused tbl[] = {
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{ PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1) },
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{ PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB0) },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, tbl);
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MODULE_DESCRIPTION("Microchip 10BASE-T1S PHYs driver");
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MODULE_AUTHOR("Ramón Nordin Rodriguez");
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MODULE_LICENSE("GPL");
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