559 lines
13 KiB
C
559 lines
13 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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//
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// Copyright (c) 2018 BayLibre, SAS.
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// Author: Jerome Brunet <jbrunet@baylibre.com>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include "axg-tdm.h"
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enum {
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TDM_IFACE_PAD,
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TDM_IFACE_LOOPBACK,
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};
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static unsigned int axg_tdm_slots_total(u32 *mask)
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{
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unsigned int slots = 0;
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int i;
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if (!mask)
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return 0;
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/* Count the total number of slots provided by all 4 lanes */
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for (i = 0; i < AXG_TDM_NUM_LANES; i++)
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slots += hweight32(mask[i]);
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return slots;
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}
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int axg_tdm_set_tdm_slots(struct snd_soc_dai *dai, u32 *tx_mask,
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u32 *rx_mask, unsigned int slots,
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unsigned int slot_width)
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{
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struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
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struct axg_tdm_stream *tx = (struct axg_tdm_stream *)
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dai->playback_dma_data;
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struct axg_tdm_stream *rx = (struct axg_tdm_stream *)
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dai->capture_dma_data;
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unsigned int tx_slots, rx_slots;
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unsigned int fmt = 0;
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tx_slots = axg_tdm_slots_total(tx_mask);
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rx_slots = axg_tdm_slots_total(rx_mask);
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/* We should at least have a slot for a valid interface */
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if (!tx_slots && !rx_slots) {
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dev_err(dai->dev, "interface has no slot\n");
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return -EINVAL;
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}
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iface->slots = slots;
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switch (slot_width) {
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case 0:
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slot_width = 32;
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fallthrough;
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case 32:
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fmt |= SNDRV_PCM_FMTBIT_S32_LE;
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fallthrough;
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case 24:
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fmt |= SNDRV_PCM_FMTBIT_S24_LE;
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fmt |= SNDRV_PCM_FMTBIT_S20_LE;
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fallthrough;
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case 16:
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fmt |= SNDRV_PCM_FMTBIT_S16_LE;
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fallthrough;
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case 8:
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fmt |= SNDRV_PCM_FMTBIT_S8;
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break;
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default:
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dev_err(dai->dev, "unsupported slot width: %d\n", slot_width);
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return -EINVAL;
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}
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iface->slot_width = slot_width;
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/* Amend the dai driver and let dpcm merge do its job */
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if (tx) {
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tx->mask = tx_mask;
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dai->driver->playback.channels_max = tx_slots;
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dai->driver->playback.formats = fmt;
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}
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if (rx) {
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rx->mask = rx_mask;
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dai->driver->capture.channels_max = rx_slots;
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dai->driver->capture.formats = fmt;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(axg_tdm_set_tdm_slots);
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static int axg_tdm_iface_set_sysclk(struct snd_soc_dai *dai, int clk_id,
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unsigned int freq, int dir)
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{
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struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
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int ret = -ENOTSUPP;
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if (dir == SND_SOC_CLOCK_OUT && clk_id == 0) {
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if (!iface->mclk) {
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dev_warn(dai->dev, "master clock not provided\n");
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} else {
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ret = clk_set_rate(iface->mclk, freq);
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if (!ret)
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iface->mclk_rate = freq;
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}
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}
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return ret;
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}
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static int axg_tdm_iface_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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if (!iface->mclk) {
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dev_err(dai->dev, "cpu clock master: mclk missing\n");
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return -ENODEV;
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}
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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break;
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case SND_SOC_DAIFMT_CBS_CFM:
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case SND_SOC_DAIFMT_CBM_CFS:
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dev_err(dai->dev, "only CBS_CFS and CBM_CFM are supported\n");
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fallthrough;
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default:
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return -EINVAL;
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}
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iface->fmt = fmt;
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return 0;
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}
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static int axg_tdm_iface_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
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struct axg_tdm_stream *ts =
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snd_soc_dai_get_dma_data(dai, substream);
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int ret;
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if (!axg_tdm_slots_total(ts->mask)) {
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dev_err(dai->dev, "interface has not slots\n");
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return -EINVAL;
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}
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/* Apply component wide rate symmetry */
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if (snd_soc_component_active(dai->component)) {
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ret = snd_pcm_hw_constraint_single(substream->runtime,
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SNDRV_PCM_HW_PARAM_RATE,
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iface->rate);
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if (ret < 0) {
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dev_err(dai->dev,
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"can't set iface rate constraint\n");
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return ret;
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}
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}
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return 0;
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}
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static int axg_tdm_iface_set_stream(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
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struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
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unsigned int channels = params_channels(params);
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unsigned int width = params_width(params);
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/* Save rate and sample_bits for component symmetry */
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iface->rate = params_rate(params);
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/* Make sure this interface can cope with the stream */
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if (axg_tdm_slots_total(ts->mask) < channels) {
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dev_err(dai->dev, "not enough slots for channels\n");
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return -EINVAL;
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}
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if (iface->slot_width < width) {
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dev_err(dai->dev, "incompatible slots width for stream\n");
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return -EINVAL;
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}
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/* Save the parameter for tdmout/tdmin widgets */
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ts->physical_width = params_physical_width(params);
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ts->width = params_width(params);
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ts->channels = params_channels(params);
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return 0;
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}
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static int axg_tdm_iface_set_lrclk(struct snd_soc_dai *dai,
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struct snd_pcm_hw_params *params)
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{
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struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
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unsigned int ratio_num;
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int ret;
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ret = clk_set_rate(iface->lrclk, params_rate(params));
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if (ret) {
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dev_err(dai->dev, "setting sample clock failed: %d\n", ret);
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return ret;
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}
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switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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case SND_SOC_DAIFMT_LEFT_J:
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case SND_SOC_DAIFMT_RIGHT_J:
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/* 50% duty cycle ratio */
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ratio_num = 1;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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case SND_SOC_DAIFMT_DSP_B:
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/*
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* A zero duty cycle ratio will result in setting the mininum
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* ratio possible which, for this clock, is 1 cycle of the
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* parent bclk clock high and the rest low, This is exactly
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* what we want here.
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*/
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ratio_num = 0;
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break;
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default:
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return -EINVAL;
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}
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ret = clk_set_duty_cycle(iface->lrclk, ratio_num, 2);
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if (ret) {
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dev_err(dai->dev,
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"setting sample clock duty cycle failed: %d\n", ret);
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return ret;
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}
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/* Set sample clock inversion */
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ret = clk_set_phase(iface->lrclk,
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axg_tdm_lrclk_invert(iface->fmt) ? 180 : 0);
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if (ret) {
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dev_err(dai->dev,
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"setting sample clock phase failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int axg_tdm_iface_set_sclk(struct snd_soc_dai *dai,
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struct snd_pcm_hw_params *params)
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{
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struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
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unsigned long srate;
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int ret;
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srate = iface->slots * iface->slot_width * params_rate(params);
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if (!iface->mclk_rate) {
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/* If no specific mclk is requested, default to bit clock * 4 */
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clk_set_rate(iface->mclk, 4 * srate);
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} else {
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/* Check if we can actually get the bit clock from mclk */
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if (iface->mclk_rate % srate) {
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dev_err(dai->dev,
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"can't derive sclk %lu from mclk %lu\n",
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srate, iface->mclk_rate);
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return -EINVAL;
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}
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}
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ret = clk_set_rate(iface->sclk, srate);
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if (ret) {
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dev_err(dai->dev, "setting bit clock failed: %d\n", ret);
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return ret;
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}
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/* Set the bit clock inversion */
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ret = clk_set_phase(iface->sclk,
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axg_tdm_sclk_invert(iface->fmt) ? 0 : 180);
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if (ret) {
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dev_err(dai->dev, "setting bit clock phase failed: %d\n", ret);
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return ret;
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}
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return ret;
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}
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static int axg_tdm_iface_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
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int ret;
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switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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case SND_SOC_DAIFMT_LEFT_J:
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case SND_SOC_DAIFMT_RIGHT_J:
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if (iface->slots > 2) {
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dev_err(dai->dev, "bad slot number for format: %d\n",
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iface->slots);
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return -EINVAL;
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}
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break;
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case SND_SOC_DAIFMT_DSP_A:
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case SND_SOC_DAIFMT_DSP_B:
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break;
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default:
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dev_err(dai->dev, "unsupported dai format\n");
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return -EINVAL;
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}
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ret = axg_tdm_iface_set_stream(substream, params, dai);
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if (ret)
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return ret;
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if ((iface->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
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SND_SOC_DAIFMT_CBS_CFS) {
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ret = axg_tdm_iface_set_sclk(dai, params);
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if (ret)
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return ret;
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ret = axg_tdm_iface_set_lrclk(dai, params);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int axg_tdm_iface_hw_free(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
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/* Stop all attached formatters */
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axg_tdm_stream_stop(ts);
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return 0;
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}
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static int axg_tdm_iface_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
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/* Force all attached formatters to update */
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return axg_tdm_stream_reset(ts);
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}
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static int axg_tdm_iface_remove_dai(struct snd_soc_dai *dai)
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{
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if (dai->capture_dma_data)
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axg_tdm_stream_free(dai->capture_dma_data);
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if (dai->playback_dma_data)
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axg_tdm_stream_free(dai->playback_dma_data);
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return 0;
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}
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static int axg_tdm_iface_probe_dai(struct snd_soc_dai *dai)
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{
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struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
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if (dai->capture_widget) {
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dai->capture_dma_data = axg_tdm_stream_alloc(iface);
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if (!dai->capture_dma_data)
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return -ENOMEM;
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}
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if (dai->playback_widget) {
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dai->playback_dma_data = axg_tdm_stream_alloc(iface);
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if (!dai->playback_dma_data) {
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axg_tdm_iface_remove_dai(dai);
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return -ENOMEM;
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}
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}
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return 0;
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}
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static const struct snd_soc_dai_ops axg_tdm_iface_ops = {
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.set_sysclk = axg_tdm_iface_set_sysclk,
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.set_fmt = axg_tdm_iface_set_fmt,
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.startup = axg_tdm_iface_startup,
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.hw_params = axg_tdm_iface_hw_params,
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.prepare = axg_tdm_iface_prepare,
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.hw_free = axg_tdm_iface_hw_free,
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};
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/* TDM Backend DAIs */
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static const struct snd_soc_dai_driver axg_tdm_iface_dai_drv[] = {
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[TDM_IFACE_PAD] = {
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.name = "TDM Pad",
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.playback = {
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.stream_name = "Playback",
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.channels_min = 1,
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.channels_max = AXG_TDM_CHANNEL_MAX,
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.rates = AXG_TDM_RATES,
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.formats = AXG_TDM_FORMATS,
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},
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.capture = {
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.stream_name = "Capture",
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.channels_min = 1,
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.channels_max = AXG_TDM_CHANNEL_MAX,
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.rates = AXG_TDM_RATES,
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.formats = AXG_TDM_FORMATS,
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},
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.id = TDM_IFACE_PAD,
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.ops = &axg_tdm_iface_ops,
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.probe = axg_tdm_iface_probe_dai,
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.remove = axg_tdm_iface_remove_dai,
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},
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[TDM_IFACE_LOOPBACK] = {
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.name = "TDM Loopback",
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.capture = {
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.stream_name = "Loopback",
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.channels_min = 1,
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.channels_max = AXG_TDM_CHANNEL_MAX,
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.rates = AXG_TDM_RATES,
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.formats = AXG_TDM_FORMATS,
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},
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.id = TDM_IFACE_LOOPBACK,
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.ops = &axg_tdm_iface_ops,
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.probe = axg_tdm_iface_probe_dai,
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.remove = axg_tdm_iface_remove_dai,
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},
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};
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static int axg_tdm_iface_set_bias_level(struct snd_soc_component *component,
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enum snd_soc_bias_level level)
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{
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struct axg_tdm_iface *iface = snd_soc_component_get_drvdata(component);
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enum snd_soc_bias_level now =
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snd_soc_component_get_bias_level(component);
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int ret = 0;
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switch (level) {
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case SND_SOC_BIAS_PREPARE:
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if (now == SND_SOC_BIAS_STANDBY)
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ret = clk_prepare_enable(iface->mclk);
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break;
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case SND_SOC_BIAS_STANDBY:
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if (now == SND_SOC_BIAS_PREPARE)
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clk_disable_unprepare(iface->mclk);
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break;
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case SND_SOC_BIAS_OFF:
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case SND_SOC_BIAS_ON:
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break;
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}
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return ret;
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}
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static const struct snd_soc_component_driver axg_tdm_iface_component_drv = {
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.set_bias_level = axg_tdm_iface_set_bias_level,
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};
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static const struct of_device_id axg_tdm_iface_of_match[] = {
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{ .compatible = "amlogic,axg-tdm-iface", },
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{}
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};
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MODULE_DEVICE_TABLE(of, axg_tdm_iface_of_match);
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static int axg_tdm_iface_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct snd_soc_dai_driver *dai_drv;
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struct axg_tdm_iface *iface;
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int ret, i;
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iface = devm_kzalloc(dev, sizeof(*iface), GFP_KERNEL);
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if (!iface)
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return -ENOMEM;
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platform_set_drvdata(pdev, iface);
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/*
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* Duplicate dai driver: depending on the slot masks configuration
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* We'll change the number of channel provided by DAI stream, so dpcm
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* channel merge can be done properly
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*/
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dai_drv = devm_kcalloc(dev, ARRAY_SIZE(axg_tdm_iface_dai_drv),
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sizeof(*dai_drv), GFP_KERNEL);
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if (!dai_drv)
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return -ENOMEM;
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|
for (i = 0; i < ARRAY_SIZE(axg_tdm_iface_dai_drv); i++)
|
|
memcpy(&dai_drv[i], &axg_tdm_iface_dai_drv[i],
|
|
sizeof(*dai_drv));
|
|
|
|
/* Bit clock provided on the pad */
|
|
iface->sclk = devm_clk_get(dev, "sclk");
|
|
if (IS_ERR(iface->sclk)) {
|
|
ret = PTR_ERR(iface->sclk);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "failed to get sclk: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
/* Sample clock provided on the pad */
|
|
iface->lrclk = devm_clk_get(dev, "lrclk");
|
|
if (IS_ERR(iface->lrclk)) {
|
|
ret = PTR_ERR(iface->lrclk);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "failed to get lrclk: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* mclk maybe be missing when the cpu dai is in slave mode and
|
|
* the codec does not require it to provide a master clock.
|
|
* At this point, ignore the error if mclk is missing. We'll
|
|
* throw an error if the cpu dai is master and mclk is missing
|
|
*/
|
|
iface->mclk = devm_clk_get(dev, "mclk");
|
|
if (IS_ERR(iface->mclk)) {
|
|
ret = PTR_ERR(iface->mclk);
|
|
if (ret == -ENOENT) {
|
|
iface->mclk = NULL;
|
|
} else {
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "failed to get mclk: %d\n", ret);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return devm_snd_soc_register_component(dev,
|
|
&axg_tdm_iface_component_drv, dai_drv,
|
|
ARRAY_SIZE(axg_tdm_iface_dai_drv));
|
|
}
|
|
|
|
static struct platform_driver axg_tdm_iface_pdrv = {
|
|
.probe = axg_tdm_iface_probe,
|
|
.driver = {
|
|
.name = "axg-tdm-iface",
|
|
.of_match_table = axg_tdm_iface_of_match,
|
|
},
|
|
};
|
|
module_platform_driver(axg_tdm_iface_pdrv);
|
|
|
|
MODULE_DESCRIPTION("Amlogic AXG TDM interface driver");
|
|
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
|
|
MODULE_LICENSE("GPL v2");
|