In general, PLL has VCO (= Voltage controlled oscillator),
one of the very important electronic feature called as "jitter"
is related to this VCO.
In academic generalism, VCO should be maximum to be more small jitter.
In high frequency clock, jitter will be large impact.
Thus, selecting Hi VCO is general theory.
fin fvco fout fclkout
in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out
+-> | | |
| |
+-----------------[1/N]<-------------+
fclkout = fvco / P / FDPLL -- (1)
In PD, it will loop until fin/M = fvco/P/N
fvco = fin * P * N / M -- (2)
(1) + (2) indicates
fclkout = fin * N / M / FDPLL
In this device, N = (n + 1), M = (m + 1), P = 2, FDPLL = (fdpll + 1).
fclkout = fin * (n + 1) / (m + 1) / (fdpll + 1)
This is the datasheet formula.
One note here is that it should be 2kHz < fvco < 4096MHz
To be smaller jitter, fvco should be maximum,
in other words, N as large as possible, M as small as possible driver
should select. Here, basically M=1.
This patch do it.
Reported-by: HIROSHI INOSE <hiroshi.inose.rb@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[Small clarifications in comments, renamed finnm to fout]
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
0bc69592ab