844 lines
21 KiB
C
844 lines
21 KiB
C
/**
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* Copyright (C) 2005 - 2010 ServerEngines
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation. The full GNU General
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* Public License is included in this distribution in the file called COPYING.
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*
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* Written by: Jayamohan Kallickal (jayamohank@serverengines.com)
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*
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* Contact Information:
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* linux-drivers@serverengines.com
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*
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* ServerEngines
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* 209 N. Fair Oaks Ave
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* Sunnyvale, CA 94085
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*
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*/
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#ifndef _BEISCSI_MAIN_
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#define _BEISCSI_MAIN_
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/in.h>
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#include <scsi/scsi.h>
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#include <scsi/scsi_cmnd.h>
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#include <scsi/scsi_device.h>
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#include <scsi/scsi_host.h>
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#include <scsi/iscsi_proto.h>
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#include <scsi/libiscsi.h>
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#include <scsi/scsi_transport_iscsi.h>
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#include "be.h"
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#define DRV_NAME "be2iscsi"
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#define BUILD_STR "2.0.527.0"
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#define BE_NAME "ServerEngines BladeEngine2" \
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"Linux iSCSI Driver version" BUILD_STR
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#define DRV_DESC BE_NAME " " "Driver"
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#define BE_VENDOR_ID 0x19A2
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/* DEVICE ID's for BE2 */
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#define BE_DEVICE_ID1 0x212
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#define OC_DEVICE_ID1 0x702
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#define OC_DEVICE_ID2 0x703
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/* DEVICE ID's for BE3 */
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#define BE_DEVICE_ID2 0x222
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#define OC_DEVICE_ID3 0x712
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#define BE2_IO_DEPTH 1024
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#define BE2_MAX_SESSIONS 256
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#define BE2_CMDS_PER_CXN 128
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#define BE2_TMFS 16
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#define BE2_NOPOUT_REQ 16
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#define BE2_SGE 32
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#define BE2_DEFPDU_HDR_SZ 64
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#define BE2_DEFPDU_DATA_SZ 8192
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#define MAX_CPUS 31
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#define BEISCSI_SGLIST_ELEMENTS 30
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#define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
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#define BEISCSI_MAX_SECTORS 256 /* scsi_host->max_sectors */
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#define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
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#define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
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#define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
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#define BEISCSI_MAX_FRAGS_INIT 192
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#define BE_NUM_MSIX_ENTRIES 1
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#define MPU_EP_SEMAPHORE 0xac
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#define BE_SENSE_INFO_SIZE 258
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#define BE_ISCSI_PDU_HEADER_SIZE 64
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#define BE_MIN_MEM_SIZE 16384
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#define MAX_CMD_SZ 65536
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#define IIOC_SCSI_DATA 0x05 /* Write Operation */
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#define DBG_LVL 0x00000001
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#define DBG_LVL_1 0x00000001
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#define DBG_LVL_2 0x00000002
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#define DBG_LVL_3 0x00000004
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#define DBG_LVL_4 0x00000008
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#define DBG_LVL_5 0x00000010
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#define DBG_LVL_6 0x00000020
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#define DBG_LVL_7 0x00000040
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#define DBG_LVL_8 0x00000080
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#define SE_DEBUG(debug_mask, fmt, args...) \
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do { \
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if (debug_mask & DBG_LVL) { \
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printk(KERN_ERR "(%s():%d):", __func__, __LINE__);\
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printk(fmt, ##args); \
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} \
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} while (0);
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#define BE_ADAPTER_UP 0x00000000
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#define BE_ADAPTER_LINK_DOWN 0x00000001
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/**
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* hardware needs the async PDU buffers to be posted in multiples of 8
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* So have atleast 8 of them by default
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*/
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#define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx)
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/********* Memory BAR register ************/
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#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
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/**
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* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
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* Disable" may still globally block interrupts in addition to individual
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* interrupt masks; a mechanism for the device driver to block all interrupts
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* atomically without having to arbitrate for the PCI Interrupt Disable bit
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* with the OS.
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*/
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#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
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/********* ISR0 Register offset **********/
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#define CEV_ISR0_OFFSET 0xC18
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#define CEV_ISR_SIZE 4
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/**
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* Macros for reading/writing a protection domain or CSR registers
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* in BladeEngine.
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*/
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#define DB_TXULP0_OFFSET 0x40
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#define DB_RXULP0_OFFSET 0xA0
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/********* Event Q door bell *************/
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#define DB_EQ_OFFSET DB_CQ_OFFSET
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#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
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/* Clear the interrupt for this eq */
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#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
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/* Must be 1 */
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#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
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/* Number of event entries processed */
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#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
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/* Rearm bit */
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#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
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/********* Compl Q door bell *************/
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#define DB_CQ_OFFSET 0x120
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#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
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/* Number of event entries processed */
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#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
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/* Rearm bit */
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#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
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#define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
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#define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
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(GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
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#define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
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(GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
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#define PAGES_REQUIRED(x) \
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((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
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enum be_mem_enum {
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HWI_MEM_ADDN_CONTEXT,
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HWI_MEM_WRB,
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HWI_MEM_WRBH,
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HWI_MEM_SGLH,
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HWI_MEM_SGE,
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HWI_MEM_ASYNC_HEADER_BUF, /* 5 */
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HWI_MEM_ASYNC_DATA_BUF,
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HWI_MEM_ASYNC_HEADER_RING,
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HWI_MEM_ASYNC_DATA_RING,
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HWI_MEM_ASYNC_HEADER_HANDLE,
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HWI_MEM_ASYNC_DATA_HANDLE, /* 10 */
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HWI_MEM_ASYNC_PDU_CONTEXT,
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ISCSI_MEM_GLOBAL_HEADER,
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SE_MEM_MAX
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};
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struct be_bus_address32 {
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unsigned int address_lo;
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unsigned int address_hi;
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};
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struct be_bus_address64 {
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unsigned long long address;
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};
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struct be_bus_address {
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union {
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struct be_bus_address32 a32;
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struct be_bus_address64 a64;
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} u;
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};
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struct mem_array {
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struct be_bus_address bus_address; /* Bus address of location */
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void *virtual_address; /* virtual address to the location */
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unsigned int size; /* Size required by memory block */
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};
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struct be_mem_descriptor {
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unsigned int index; /* Index of this memory parameter */
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unsigned int category; /* type indicates cached/non-cached */
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unsigned int num_elements; /* number of elements in this
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* descriptor
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*/
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unsigned int alignment_mask; /* Alignment mask for this block */
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unsigned int size_in_bytes; /* Size required by memory block */
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struct mem_array *mem_array;
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};
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struct sgl_handle {
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unsigned int sgl_index;
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unsigned int type;
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unsigned int cid;
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struct iscsi_task *task;
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struct iscsi_sge *pfrag;
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};
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struct hba_parameters {
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unsigned int ios_per_ctrl;
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unsigned int cxns_per_ctrl;
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unsigned int asyncpdus_per_ctrl;
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unsigned int icds_per_ctrl;
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unsigned int num_sge_per_io;
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unsigned int defpdu_hdr_sz;
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unsigned int defpdu_data_sz;
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unsigned int num_cq_entries;
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unsigned int num_eq_entries;
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unsigned int wrbs_per_cxn;
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unsigned int crashmode;
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unsigned int hba_num;
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unsigned int mgmt_ws_sz;
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unsigned int hwi_ws_sz;
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unsigned int eto;
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unsigned int ldto;
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unsigned int dbg_flags;
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unsigned int num_cxn;
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unsigned int eq_timer;
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/**
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* These are calculated from other params. They're here
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* for debug purposes
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*/
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unsigned int num_mcc_pages;
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unsigned int num_mcc_cq_pages;
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unsigned int num_cq_pages;
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unsigned int num_eq_pages;
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unsigned int num_async_pdu_buf_pages;
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unsigned int num_async_pdu_buf_sgl_pages;
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unsigned int num_async_pdu_buf_cq_pages;
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unsigned int num_async_pdu_hdr_pages;
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unsigned int num_async_pdu_hdr_sgl_pages;
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unsigned int num_async_pdu_hdr_cq_pages;
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unsigned int num_sge;
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};
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struct beiscsi_hba {
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struct hba_parameters params;
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struct hwi_controller *phwi_ctrlr;
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unsigned int mem_req[SE_MEM_MAX];
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/* PCI BAR mapped addresses */
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u8 __iomem *csr_va; /* CSR */
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u8 __iomem *db_va; /* Door Bell */
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u8 __iomem *pci_va; /* PCI Config */
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struct be_bus_address csr_pa; /* CSR */
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struct be_bus_address db_pa; /* CSR */
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struct be_bus_address pci_pa; /* CSR */
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/* PCI representation of our HBA */
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struct pci_dev *pcidev;
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unsigned int state;
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unsigned short asic_revision;
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unsigned int num_cpus;
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unsigned int nxt_cqid;
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struct msix_entry msix_entries[MAX_CPUS + 1];
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bool msix_enabled;
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struct be_mem_descriptor *init_mem;
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unsigned short io_sgl_alloc_index;
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unsigned short io_sgl_free_index;
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unsigned short io_sgl_hndl_avbl;
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struct sgl_handle **io_sgl_hndl_base;
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struct sgl_handle **sgl_hndl_array;
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unsigned short eh_sgl_alloc_index;
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unsigned short eh_sgl_free_index;
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unsigned short eh_sgl_hndl_avbl;
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struct sgl_handle **eh_sgl_hndl_base;
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spinlock_t io_sgl_lock;
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spinlock_t mgmt_sgl_lock;
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spinlock_t isr_lock;
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unsigned int age;
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unsigned short avlbl_cids;
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unsigned short cid_alloc;
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unsigned short cid_free;
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struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2];
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struct list_head hba_queue;
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unsigned short *cid_array;
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struct iscsi_endpoint **ep_array;
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struct Scsi_Host *shost;
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struct {
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/**
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* group together since they are used most frequently
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* for cid to cri conversion
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*/
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unsigned int iscsi_cid_start;
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unsigned int phys_port;
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unsigned int isr_offset;
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unsigned int iscsi_icd_start;
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unsigned int iscsi_cid_count;
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unsigned int iscsi_icd_count;
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unsigned int pci_function;
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unsigned short cid_alloc;
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unsigned short cid_free;
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unsigned short avlbl_cids;
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unsigned short iscsi_features;
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spinlock_t cid_lock;
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} fw_config;
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u8 mac_address[ETH_ALEN];
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unsigned short todo_cq;
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unsigned short todo_mcc_cq;
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char wq_name[20];
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struct workqueue_struct *wq; /* The actuak work queue */
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struct work_struct work_cqs; /* The work being queued */
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struct be_ctrl_info ctrl;
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unsigned int generation;
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};
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struct beiscsi_session {
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struct pci_pool *bhs_pool;
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};
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/**
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* struct beiscsi_conn - iscsi connection structure
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*/
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struct beiscsi_conn {
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struct iscsi_conn *conn;
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struct beiscsi_hba *phba;
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u32 exp_statsn;
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u32 beiscsi_conn_cid;
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struct beiscsi_endpoint *ep;
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unsigned short login_in_progress;
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struct sgl_handle *plogin_sgl_handle;
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struct beiscsi_session *beiscsi_sess;
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struct iscsi_task *task;
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};
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/* This structure is used by the chip */
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struct pdu_data_out {
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u32 dw[12];
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};
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/**
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* Pseudo amap definition in which each bit of the actual structure is defined
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* as a byte: used to calculate offset/shift/mask of each field
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*/
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struct amap_pdu_data_out {
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u8 opcode[6]; /* opcode */
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u8 rsvd0[2]; /* should be 0 */
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u8 rsvd1[7];
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u8 final_bit; /* F bit */
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u8 rsvd2[16];
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u8 ahs_length[8]; /* no AHS */
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u8 data_len_hi[8];
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u8 data_len_lo[16]; /* DataSegmentLength */
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u8 lun[64];
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u8 itt[32]; /* ITT; initiator task tag */
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u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
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u8 rsvd3[32];
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u8 exp_stat_sn[32];
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u8 rsvd4[32];
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u8 data_sn[32];
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u8 buffer_offset[32];
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u8 rsvd5[32];
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};
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struct be_cmd_bhs {
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struct iscsi_cmd iscsi_hdr;
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unsigned char pad1[16];
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struct pdu_data_out iscsi_data_pdu;
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unsigned char pad2[BE_SENSE_INFO_SIZE -
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sizeof(struct pdu_data_out)];
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};
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struct beiscsi_io_task {
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struct wrb_handle *pwrb_handle;
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struct sgl_handle *psgl_handle;
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struct beiscsi_conn *conn;
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struct scsi_cmnd *scsi_cmnd;
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unsigned int cmd_sn;
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unsigned int flags;
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unsigned short cid;
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unsigned short header_len;
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itt_t libiscsi_itt;
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struct be_cmd_bhs *cmd_bhs;
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struct be_bus_address bhs_pa;
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unsigned short bhs_len;
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};
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struct be_nonio_bhs {
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struct iscsi_hdr iscsi_hdr;
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unsigned char pad1[16];
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struct pdu_data_out iscsi_data_pdu;
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unsigned char pad2[BE_SENSE_INFO_SIZE -
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sizeof(struct pdu_data_out)];
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};
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struct be_status_bhs {
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struct iscsi_cmd iscsi_hdr;
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unsigned char pad1[16];
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/**
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* The plus 2 below is to hold the sense info length that gets
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* DMA'ed by RxULP
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*/
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unsigned char sense_info[BE_SENSE_INFO_SIZE];
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};
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struct iscsi_sge {
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u32 dw[4];
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};
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/**
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* Pseudo amap definition in which each bit of the actual structure is defined
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* as a byte: used to calculate offset/shift/mask of each field
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*/
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struct amap_iscsi_sge {
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u8 addr_hi[32];
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u8 addr_lo[32];
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u8 sge_offset[22]; /* DWORD 2 */
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u8 rsvd0[9]; /* DWORD 2 */
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u8 last_sge; /* DWORD 2 */
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u8 len[17]; /* DWORD 3 */
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u8 rsvd1[15]; /* DWORD 3 */
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};
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struct beiscsi_offload_params {
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u32 dw[5];
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};
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#define OFFLD_PARAMS_ERL 0x00000003
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#define OFFLD_PARAMS_DDE 0x00000004
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#define OFFLD_PARAMS_HDE 0x00000008
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#define OFFLD_PARAMS_IR2T 0x00000010
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#define OFFLD_PARAMS_IMD 0x00000020
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/**
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* Pseudo amap definition in which each bit of the actual structure is defined
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* as a byte: used to calculate offset/shift/mask of each field
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*/
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struct amap_beiscsi_offload_params {
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u8 max_burst_length[32];
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u8 max_send_data_segment_length[32];
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u8 first_burst_length[32];
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u8 erl[2];
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u8 dde[1];
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u8 hde[1];
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u8 ir2t[1];
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u8 imd[1];
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u8 pad[26];
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u8 exp_statsn[32];
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};
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/* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
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struct beiscsi_hba *phba, struct sol_cqe *psol);*/
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struct async_pdu_handle {
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struct list_head link;
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struct be_bus_address pa;
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void *pbuffer;
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unsigned int consumed;
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unsigned char index;
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unsigned char is_header;
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unsigned short cri;
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unsigned long buffer_len;
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};
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struct hwi_async_entry {
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struct {
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unsigned char hdr_received;
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unsigned char hdr_len;
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unsigned short bytes_received;
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unsigned int bytes_needed;
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struct list_head list;
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} wait_queue;
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struct list_head header_busy_list;
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struct list_head data_busy_list;
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};
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#define BE_MIN_ASYNC_ENTRIES 128
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struct hwi_async_pdu_context {
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struct {
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struct be_bus_address pa_base;
|
|
void *va_base;
|
|
void *ring_base;
|
|
struct async_pdu_handle *handle_base;
|
|
|
|
unsigned int host_write_ptr;
|
|
unsigned int ep_read_ptr;
|
|
unsigned int writables;
|
|
|
|
unsigned int free_entries;
|
|
unsigned int busy_entries;
|
|
unsigned int buffer_size;
|
|
unsigned int num_entries;
|
|
|
|
struct list_head free_list;
|
|
} async_header;
|
|
|
|
struct {
|
|
struct be_bus_address pa_base;
|
|
void *va_base;
|
|
void *ring_base;
|
|
struct async_pdu_handle *handle_base;
|
|
|
|
unsigned int host_write_ptr;
|
|
unsigned int ep_read_ptr;
|
|
unsigned int writables;
|
|
|
|
unsigned int free_entries;
|
|
unsigned int busy_entries;
|
|
unsigned int buffer_size;
|
|
struct list_head free_list;
|
|
unsigned int num_entries;
|
|
} async_data;
|
|
|
|
/**
|
|
* This is a varying size list! Do not add anything
|
|
* after this entry!!
|
|
*/
|
|
struct hwi_async_entry async_entry[BE_MIN_ASYNC_ENTRIES];
|
|
};
|
|
|
|
#define PDUCQE_CODE_MASK 0x0000003F
|
|
#define PDUCQE_DPL_MASK 0xFFFF0000
|
|
#define PDUCQE_INDEX_MASK 0x0000FFFF
|
|
|
|
struct i_t_dpdu_cqe {
|
|
u32 dw[4];
|
|
} __packed;
|
|
|
|
/**
|
|
* Pseudo amap definition in which each bit of the actual structure is defined
|
|
* as a byte: used to calculate offset/shift/mask of each field
|
|
*/
|
|
struct amap_i_t_dpdu_cqe {
|
|
u8 db_addr_hi[32];
|
|
u8 db_addr_lo[32];
|
|
u8 code[6];
|
|
u8 cid[10];
|
|
u8 dpl[16];
|
|
u8 index[16];
|
|
u8 num_cons[10];
|
|
u8 rsvd0[4];
|
|
u8 final;
|
|
u8 valid;
|
|
} __packed;
|
|
|
|
#define CQE_VALID_MASK 0x80000000
|
|
#define CQE_CODE_MASK 0x0000003F
|
|
#define CQE_CID_MASK 0x0000FFC0
|
|
|
|
#define EQE_VALID_MASK 0x00000001
|
|
#define EQE_MAJORCODE_MASK 0x0000000E
|
|
#define EQE_RESID_MASK 0xFFFF0000
|
|
|
|
struct be_eq_entry {
|
|
u32 dw[1];
|
|
} __packed;
|
|
|
|
/**
|
|
* Pseudo amap definition in which each bit of the actual structure is defined
|
|
* as a byte: used to calculate offset/shift/mask of each field
|
|
*/
|
|
struct amap_eq_entry {
|
|
u8 valid; /* DWORD 0 */
|
|
u8 major_code[3]; /* DWORD 0 */
|
|
u8 minor_code[12]; /* DWORD 0 */
|
|
u8 resource_id[16]; /* DWORD 0 */
|
|
|
|
} __packed;
|
|
|
|
struct cq_db {
|
|
u32 dw[1];
|
|
} __packed;
|
|
|
|
/**
|
|
* Pseudo amap definition in which each bit of the actual structure is defined
|
|
* as a byte: used to calculate offset/shift/mask of each field
|
|
*/
|
|
struct amap_cq_db {
|
|
u8 qid[10];
|
|
u8 event[1];
|
|
u8 rsvd0[5];
|
|
u8 num_popped[13];
|
|
u8 rearm[1];
|
|
u8 rsvd1[2];
|
|
} __packed;
|
|
|
|
void beiscsi_process_eq(struct beiscsi_hba *phba);
|
|
|
|
struct iscsi_wrb {
|
|
u32 dw[16];
|
|
} __packed;
|
|
|
|
#define WRB_TYPE_MASK 0xF0000000
|
|
|
|
/**
|
|
* Pseudo amap definition in which each bit of the actual structure is defined
|
|
* as a byte: used to calculate offset/shift/mask of each field
|
|
*/
|
|
struct amap_iscsi_wrb {
|
|
u8 lun[14]; /* DWORD 0 */
|
|
u8 lt; /* DWORD 0 */
|
|
u8 invld; /* DWORD 0 */
|
|
u8 wrb_idx[8]; /* DWORD 0 */
|
|
u8 dsp; /* DWORD 0 */
|
|
u8 dmsg; /* DWORD 0 */
|
|
u8 undr_run; /* DWORD 0 */
|
|
u8 over_run; /* DWORD 0 */
|
|
u8 type[4]; /* DWORD 0 */
|
|
u8 ptr2nextwrb[8]; /* DWORD 1 */
|
|
u8 r2t_exp_dtl[24]; /* DWORD 1 */
|
|
u8 sgl_icd_idx[12]; /* DWORD 2 */
|
|
u8 rsvd0[20]; /* DWORD 2 */
|
|
u8 exp_data_sn[32]; /* DWORD 3 */
|
|
u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
|
|
u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
|
|
u8 cmdsn_itt[32]; /* DWORD 6 */
|
|
u8 dif_ref_tag[32]; /* DWORD 7 */
|
|
u8 sge0_addr_hi[32]; /* DWORD 8 */
|
|
u8 sge0_addr_lo[32]; /* DWORD 9 */
|
|
u8 sge0_offset[22]; /* DWORD 10 */
|
|
u8 pbs; /* DWORD 10 */
|
|
u8 dif_mode[2]; /* DWORD 10 */
|
|
u8 rsvd1[6]; /* DWORD 10 */
|
|
u8 sge0_last; /* DWORD 10 */
|
|
u8 sge0_len[17]; /* DWORD 11 */
|
|
u8 dif_meta_tag[14]; /* DWORD 11 */
|
|
u8 sge0_in_ddr; /* DWORD 11 */
|
|
u8 sge1_addr_hi[32]; /* DWORD 12 */
|
|
u8 sge1_addr_lo[32]; /* DWORD 13 */
|
|
u8 sge1_r2t_offset[22]; /* DWORD 14 */
|
|
u8 rsvd2[9]; /* DWORD 14 */
|
|
u8 sge1_last; /* DWORD 14 */
|
|
u8 sge1_len[17]; /* DWORD 15 */
|
|
u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
|
|
u8 rsvd3[2]; /* DWORD 15 */
|
|
u8 sge1_in_ddr; /* DWORD 15 */
|
|
|
|
} __packed;
|
|
|
|
struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
|
|
void
|
|
free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
|
|
|
|
void beiscsi_process_all_cqs(struct work_struct *work);
|
|
|
|
struct pdu_nop_out {
|
|
u32 dw[12];
|
|
};
|
|
|
|
/**
|
|
* Pseudo amap definition in which each bit of the actual structure is defined
|
|
* as a byte: used to calculate offset/shift/mask of each field
|
|
*/
|
|
struct amap_pdu_nop_out {
|
|
u8 opcode[6]; /* opcode 0x00 */
|
|
u8 i_bit; /* I Bit */
|
|
u8 x_bit; /* reserved; should be 0 */
|
|
u8 fp_bit_filler1[7];
|
|
u8 f_bit; /* always 1 */
|
|
u8 reserved1[16];
|
|
u8 ahs_length[8]; /* no AHS */
|
|
u8 data_len_hi[8];
|
|
u8 data_len_lo[16]; /* DataSegmentLength */
|
|
u8 lun[64];
|
|
u8 itt[32]; /* initiator id for ping or 0xffffffff */
|
|
u8 ttt[32]; /* target id for ping or 0xffffffff */
|
|
u8 cmd_sn[32];
|
|
u8 exp_stat_sn[32];
|
|
u8 reserved5[128];
|
|
};
|
|
|
|
#define PDUBASE_OPCODE_MASK 0x0000003F
|
|
#define PDUBASE_DATALENHI_MASK 0x0000FF00
|
|
#define PDUBASE_DATALENLO_MASK 0xFFFF0000
|
|
|
|
struct pdu_base {
|
|
u32 dw[16];
|
|
} __packed;
|
|
|
|
/**
|
|
* Pseudo amap definition in which each bit of the actual structure is defined
|
|
* as a byte: used to calculate offset/shift/mask of each field
|
|
*/
|
|
struct amap_pdu_base {
|
|
u8 opcode[6];
|
|
u8 i_bit; /* immediate bit */
|
|
u8 x_bit; /* reserved, always 0 */
|
|
u8 reserved1[24]; /* opcode-specific fields */
|
|
u8 ahs_length[8]; /* length units is 4 byte words */
|
|
u8 data_len_hi[8];
|
|
u8 data_len_lo[16]; /* DatasegmentLength */
|
|
u8 lun[64]; /* lun or opcode-specific fields */
|
|
u8 itt[32]; /* initiator task tag */
|
|
u8 reserved4[224];
|
|
};
|
|
|
|
struct iscsi_target_context_update_wrb {
|
|
u32 dw[16];
|
|
} __packed;
|
|
|
|
/**
|
|
* Pseudo amap definition in which each bit of the actual structure is defined
|
|
* as a byte: used to calculate offset/shift/mask of each field
|
|
*/
|
|
struct amap_iscsi_target_context_update_wrb {
|
|
u8 lun[14]; /* DWORD 0 */
|
|
u8 lt; /* DWORD 0 */
|
|
u8 invld; /* DWORD 0 */
|
|
u8 wrb_idx[8]; /* DWORD 0 */
|
|
u8 dsp; /* DWORD 0 */
|
|
u8 dmsg; /* DWORD 0 */
|
|
u8 undr_run; /* DWORD 0 */
|
|
u8 over_run; /* DWORD 0 */
|
|
u8 type[4]; /* DWORD 0 */
|
|
u8 ptr2nextwrb[8]; /* DWORD 1 */
|
|
u8 max_burst_length[19]; /* DWORD 1 */
|
|
u8 rsvd0[5]; /* DWORD 1 */
|
|
u8 rsvd1[15]; /* DWORD 2 */
|
|
u8 max_send_data_segment_length[17]; /* DWORD 2 */
|
|
u8 first_burst_length[14]; /* DWORD 3 */
|
|
u8 rsvd2[2]; /* DWORD 3 */
|
|
u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
|
|
u8 rsvd3[5]; /* DWORD 3 */
|
|
u8 session_state[3]; /* DWORD 3 */
|
|
u8 rsvd4[16]; /* DWORD 4 */
|
|
u8 tx_jumbo; /* DWORD 4 */
|
|
u8 hde; /* DWORD 4 */
|
|
u8 dde; /* DWORD 4 */
|
|
u8 erl[2]; /* DWORD 4 */
|
|
u8 domain_id[5]; /* DWORD 4 */
|
|
u8 mode; /* DWORD 4 */
|
|
u8 imd; /* DWORD 4 */
|
|
u8 ir2t; /* DWORD 4 */
|
|
u8 notpredblq[2]; /* DWORD 4 */
|
|
u8 compltonack; /* DWORD 4 */
|
|
u8 stat_sn[32]; /* DWORD 5 */
|
|
u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
|
|
u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
|
|
u8 pad_addr_hi[32]; /* DWORD 8 */
|
|
u8 pad_addr_lo[32]; /* DWORD 9 */
|
|
u8 rsvd5[32]; /* DWORD 10 */
|
|
u8 rsvd6[32]; /* DWORD 11 */
|
|
u8 rsvd7[32]; /* DWORD 12 */
|
|
u8 rsvd8[32]; /* DWORD 13 */
|
|
u8 rsvd9[32]; /* DWORD 14 */
|
|
u8 rsvd10[32]; /* DWORD 15 */
|
|
|
|
} __packed;
|
|
|
|
struct be_ring {
|
|
u32 pages; /* queue size in pages */
|
|
u32 id; /* queue id assigned by beklib */
|
|
u32 num; /* number of elements in queue */
|
|
u32 cidx; /* consumer index */
|
|
u32 pidx; /* producer index -- not used by most rings */
|
|
u32 item_size; /* size in bytes of one object */
|
|
|
|
void *va; /* The virtual address of the ring. This
|
|
* should be last to allow 32 & 64 bit debugger
|
|
* extensions to work.
|
|
*/
|
|
};
|
|
|
|
struct hwi_wrb_context {
|
|
struct list_head wrb_handle_list;
|
|
struct list_head wrb_handle_drvr_list;
|
|
struct wrb_handle **pwrb_handle_base;
|
|
struct wrb_handle **pwrb_handle_basestd;
|
|
struct iscsi_wrb *plast_wrb;
|
|
unsigned short alloc_index;
|
|
unsigned short free_index;
|
|
unsigned short wrb_handles_available;
|
|
unsigned short cid;
|
|
};
|
|
|
|
struct hwi_controller {
|
|
struct list_head io_sgl_list;
|
|
struct list_head eh_sgl_list;
|
|
struct sgl_handle *psgl_handle_base;
|
|
unsigned int wrb_mem_index;
|
|
|
|
struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2];
|
|
struct mcc_wrb *pmcc_wrb_base;
|
|
struct be_ring default_pdu_hdr;
|
|
struct be_ring default_pdu_data;
|
|
struct hwi_context_memory *phwi_ctxt;
|
|
};
|
|
|
|
enum hwh_type_enum {
|
|
HWH_TYPE_IO = 1,
|
|
HWH_TYPE_LOGOUT = 2,
|
|
HWH_TYPE_TMF = 3,
|
|
HWH_TYPE_NOP = 4,
|
|
HWH_TYPE_IO_RD = 5,
|
|
HWH_TYPE_LOGIN = 11,
|
|
HWH_TYPE_INVALID = 0xFFFFFFFF
|
|
};
|
|
|
|
struct wrb_handle {
|
|
enum hwh_type_enum type;
|
|
unsigned short wrb_index;
|
|
unsigned short nxt_wrb_index;
|
|
|
|
struct iscsi_task *pio_handle;
|
|
struct iscsi_wrb *pwrb;
|
|
};
|
|
|
|
struct hwi_context_memory {
|
|
/* Adaptive interrupt coalescing (AIC) info */
|
|
u16 min_eqd; /* in usecs */
|
|
u16 max_eqd; /* in usecs */
|
|
u16 cur_eqd; /* in usecs */
|
|
struct be_eq_obj be_eq[MAX_CPUS];
|
|
struct be_queue_info be_cq[MAX_CPUS];
|
|
|
|
struct be_queue_info be_def_hdrq;
|
|
struct be_queue_info be_def_dataq;
|
|
|
|
struct be_queue_info be_wrbq[BE2_MAX_SESSIONS];
|
|
struct be_mcc_wrb_context *pbe_mcc_context;
|
|
|
|
struct hwi_async_pdu_context *pasync_ctx;
|
|
};
|
|
|
|
#endif
|