270 lines
7.9 KiB
C
270 lines
7.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_PMU_H
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#define __KVM_X86_PMU_H
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#include <linux/nospec.h>
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#define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu)
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#define pmu_to_vcpu(pmu) (container_of((pmu), struct kvm_vcpu, arch.pmu))
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#define pmc_to_pmu(pmc) (&(pmc)->vcpu->arch.pmu)
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#define MSR_IA32_MISC_ENABLE_PMU_RO_MASK (MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL | \
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MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)
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/* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */
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#define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf)
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#define VMWARE_BACKDOOR_PMC_HOST_TSC 0x10000
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#define VMWARE_BACKDOOR_PMC_REAL_TIME 0x10001
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#define VMWARE_BACKDOOR_PMC_APPARENT_TIME 0x10002
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struct kvm_pmu_ops {
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bool (*hw_event_available)(struct kvm_pmc *pmc);
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struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx);
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struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu,
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unsigned int idx, u64 *mask);
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struct kvm_pmc *(*msr_idx_to_pmc)(struct kvm_vcpu *vcpu, u32 msr);
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bool (*is_valid_rdpmc_ecx)(struct kvm_vcpu *vcpu, unsigned int idx);
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bool (*is_valid_msr)(struct kvm_vcpu *vcpu, u32 msr);
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int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
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int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
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void (*refresh)(struct kvm_vcpu *vcpu);
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void (*init)(struct kvm_vcpu *vcpu);
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void (*reset)(struct kvm_vcpu *vcpu);
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void (*deliver_pmi)(struct kvm_vcpu *vcpu);
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void (*cleanup)(struct kvm_vcpu *vcpu);
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const u64 EVENTSEL_EVENT;
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const int MAX_NR_GP_COUNTERS;
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const int MIN_NR_GP_COUNTERS;
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};
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void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops);
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static inline bool kvm_pmu_has_perf_global_ctrl(struct kvm_pmu *pmu)
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{
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/*
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* Architecturally, Intel's SDM states that IA32_PERF_GLOBAL_CTRL is
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* supported if "CPUID.0AH: EAX[7:0] > 0", i.e. if the PMU version is
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* greater than zero. However, KVM only exposes and emulates the MSR
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* to/for the guest if the guest PMU supports at least "Architectural
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* Performance Monitoring Version 2".
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*
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* AMD's version of PERF_GLOBAL_CTRL conveniently shows up with v2.
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*/
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return pmu->version > 1;
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}
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static inline u64 pmc_bitmask(struct kvm_pmc *pmc)
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{
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struct kvm_pmu *pmu = pmc_to_pmu(pmc);
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return pmu->counter_bitmask[pmc->type];
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}
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static inline u64 pmc_read_counter(struct kvm_pmc *pmc)
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{
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u64 counter, enabled, running;
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counter = pmc->counter;
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if (pmc->perf_event && !pmc->is_paused)
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counter += perf_event_read_value(pmc->perf_event,
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&enabled, &running);
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/* FIXME: Scaling needed? */
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return counter & pmc_bitmask(pmc);
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}
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static inline void pmc_release_perf_event(struct kvm_pmc *pmc)
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{
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if (pmc->perf_event) {
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perf_event_release_kernel(pmc->perf_event);
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pmc->perf_event = NULL;
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pmc->current_config = 0;
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pmc_to_pmu(pmc)->event_count--;
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}
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}
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static inline void pmc_stop_counter(struct kvm_pmc *pmc)
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{
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if (pmc->perf_event) {
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pmc->counter = pmc_read_counter(pmc);
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pmc_release_perf_event(pmc);
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}
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}
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static inline bool pmc_is_gp(struct kvm_pmc *pmc)
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{
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return pmc->type == KVM_PMC_GP;
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}
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static inline bool pmc_is_fixed(struct kvm_pmc *pmc)
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{
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return pmc->type == KVM_PMC_FIXED;
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}
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static inline bool kvm_valid_perf_global_ctrl(struct kvm_pmu *pmu,
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u64 data)
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{
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return !(pmu->global_ctrl_mask & data);
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}
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/* returns general purpose PMC with the specified MSR. Note that it can be
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* used for both PERFCTRn and EVNTSELn; that is why it accepts base as a
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* parameter to tell them apart.
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*/
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static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr,
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u32 base)
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{
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if (msr >= base && msr < base + pmu->nr_arch_gp_counters) {
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u32 index = array_index_nospec(msr - base,
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pmu->nr_arch_gp_counters);
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return &pmu->gp_counters[index];
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}
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return NULL;
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}
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/* returns fixed PMC with the specified MSR */
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static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr)
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{
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int base = MSR_CORE_PERF_FIXED_CTR0;
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if (msr >= base && msr < base + pmu->nr_arch_fixed_counters) {
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u32 index = array_index_nospec(msr - base,
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pmu->nr_arch_fixed_counters);
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return &pmu->fixed_counters[index];
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}
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return NULL;
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}
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static inline u64 get_sample_period(struct kvm_pmc *pmc, u64 counter_value)
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{
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u64 sample_period = (-counter_value) & pmc_bitmask(pmc);
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if (!sample_period)
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sample_period = pmc_bitmask(pmc) + 1;
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return sample_period;
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}
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static inline void pmc_update_sample_period(struct kvm_pmc *pmc)
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{
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if (!pmc->perf_event || pmc->is_paused ||
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!is_sampling_event(pmc->perf_event))
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return;
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perf_event_period(pmc->perf_event,
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get_sample_period(pmc, pmc->counter));
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}
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static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc)
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{
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struct kvm_pmu *pmu = pmc_to_pmu(pmc);
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if (pmc_is_fixed(pmc))
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return fixed_ctrl_field(pmu->fixed_ctr_ctrl,
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pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3;
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return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE;
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}
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extern struct x86_pmu_capability kvm_pmu_cap;
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static inline void kvm_init_pmu_capability(const struct kvm_pmu_ops *pmu_ops)
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{
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bool is_intel = boot_cpu_data.x86_vendor == X86_VENDOR_INTEL;
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int min_nr_gp_ctrs = pmu_ops->MIN_NR_GP_COUNTERS;
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/*
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* Hybrid PMUs don't play nice with virtualization without careful
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* configuration by userspace, and KVM's APIs for reporting supported
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* vPMU features do not account for hybrid PMUs. Disable vPMU support
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* for hybrid PMUs until KVM gains a way to let userspace opt-in.
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*/
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if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
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enable_pmu = false;
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if (enable_pmu) {
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perf_get_x86_pmu_capability(&kvm_pmu_cap);
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/*
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* WARN if perf did NOT disable hardware PMU if the number of
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* architecturally required GP counters aren't present, i.e. if
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* there are a non-zero number of counters, but fewer than what
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* is architecturally required.
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*/
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if (!kvm_pmu_cap.num_counters_gp ||
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WARN_ON_ONCE(kvm_pmu_cap.num_counters_gp < min_nr_gp_ctrs))
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enable_pmu = false;
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else if (is_intel && !kvm_pmu_cap.version)
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enable_pmu = false;
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}
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if (!enable_pmu) {
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memset(&kvm_pmu_cap, 0, sizeof(kvm_pmu_cap));
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return;
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}
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kvm_pmu_cap.version = min(kvm_pmu_cap.version, 2);
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kvm_pmu_cap.num_counters_gp = min(kvm_pmu_cap.num_counters_gp,
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pmu_ops->MAX_NR_GP_COUNTERS);
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kvm_pmu_cap.num_counters_fixed = min(kvm_pmu_cap.num_counters_fixed,
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KVM_PMC_MAX_FIXED);
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}
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static inline void kvm_pmu_request_counter_reprogram(struct kvm_pmc *pmc)
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{
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set_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi);
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kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
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}
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static inline void reprogram_counters(struct kvm_pmu *pmu, u64 diff)
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{
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int bit;
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if (!diff)
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return;
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for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX)
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set_bit(bit, pmu->reprogram_pmi);
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kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu));
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}
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/*
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* Check if a PMC is enabled by comparing it against global_ctrl bits.
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*
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* If the vPMU doesn't have global_ctrl MSR, all vPMCs are enabled.
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*/
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static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc)
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{
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struct kvm_pmu *pmu = pmc_to_pmu(pmc);
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if (!kvm_pmu_has_perf_global_ctrl(pmu))
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return true;
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return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
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}
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void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu);
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void kvm_pmu_handle_event(struct kvm_vcpu *vcpu);
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int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data);
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bool kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx);
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bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr);
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int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
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int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
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void kvm_pmu_refresh(struct kvm_vcpu *vcpu);
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void kvm_pmu_reset(struct kvm_vcpu *vcpu);
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void kvm_pmu_init(struct kvm_vcpu *vcpu);
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void kvm_pmu_cleanup(struct kvm_vcpu *vcpu);
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void kvm_pmu_destroy(struct kvm_vcpu *vcpu);
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int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp);
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void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id);
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bool is_vmware_backdoor_pmc(u32 pmc_idx);
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extern struct kvm_pmu_ops intel_pmu_ops;
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extern struct kvm_pmu_ops amd_pmu_ops;
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#endif /* __KVM_X86_PMU_H */
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