306 lines
9.5 KiB
C
306 lines
9.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_MMU_H
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#define __KVM_X86_MMU_H
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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#include "cpuid.h"
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extern bool __read_mostly enable_mmio_caching;
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#define PT_WRITABLE_SHIFT 1
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#define PT_USER_SHIFT 2
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#define PT_PRESENT_MASK (1ULL << 0)
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#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
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#define PT_USER_MASK (1ULL << PT_USER_SHIFT)
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#define PT_PWT_MASK (1ULL << 3)
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#define PT_PCD_MASK (1ULL << 4)
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#define PT_ACCESSED_SHIFT 5
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#define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
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#define PT_DIRTY_SHIFT 6
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#define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
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#define PT_PAGE_SIZE_SHIFT 7
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#define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
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#define PT_PAT_MASK (1ULL << 7)
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#define PT_GLOBAL_MASK (1ULL << 8)
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#define PT64_NX_SHIFT 63
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#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
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#define PT_PAT_SHIFT 7
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#define PT_DIR_PAT_SHIFT 12
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#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
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#define PT64_ROOT_5LEVEL 5
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#define PT64_ROOT_4LEVEL 4
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#define PT32_ROOT_LEVEL 2
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#define PT32E_ROOT_LEVEL 3
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#define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \
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X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE)
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#define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP)
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#define KVM_MMU_EFER_ROLE_BITS (EFER_LME | EFER_NX)
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static __always_inline u64 rsvd_bits(int s, int e)
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{
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BUILD_BUG_ON(__builtin_constant_p(e) && __builtin_constant_p(s) && e < s);
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if (__builtin_constant_p(e))
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BUILD_BUG_ON(e > 63);
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else
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e &= 63;
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if (e < s)
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return 0;
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return ((2ULL << (e - s)) - 1) << s;
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}
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/*
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* The number of non-reserved physical address bits irrespective of features
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* that repurpose legal bits, e.g. MKTME.
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*/
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extern u8 __read_mostly shadow_phys_bits;
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static inline gfn_t kvm_mmu_max_gfn(void)
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{
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/*
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* Note that this uses the host MAXPHYADDR, not the guest's.
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* EPT/NPT cannot support GPAs that would exceed host.MAXPHYADDR;
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* assuming KVM is running on bare metal, guest accesses beyond
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* host.MAXPHYADDR will hit a #PF(RSVD) and never cause a vmexit
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* (either EPT Violation/Misconfig or #NPF), and so KVM will never
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* install a SPTE for such addresses. If KVM is running as a VM
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* itself, on the other hand, it might see a MAXPHYADDR that is less
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* than hardware's real MAXPHYADDR. Using the host MAXPHYADDR
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* disallows such SPTEs entirely and simplifies the TDP MMU.
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*/
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int max_gpa_bits = likely(tdp_enabled) ? shadow_phys_bits : 52;
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return (1ULL << (max_gpa_bits - PAGE_SHIFT)) - 1;
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}
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static inline u8 kvm_get_shadow_phys_bits(void)
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{
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/*
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* boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected
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* in CPU detection code, but the processor treats those reduced bits as
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* 'keyID' thus they are not reserved bits. Therefore KVM needs to look at
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* the physical address bits reported by CPUID.
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*/
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if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008))
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return cpuid_eax(0x80000008) & 0xff;
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/*
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* Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with
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* custom CPUID. Proceed with whatever the kernel found since these features
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* aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008).
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*/
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return boot_cpu_data.x86_phys_bits;
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}
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void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask);
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void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask);
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void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only);
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void kvm_init_mmu(struct kvm_vcpu *vcpu);
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void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
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unsigned long cr4, u64 efer, gpa_t nested_cr3);
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void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
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int huge_page_level, bool accessed_dirty,
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gpa_t new_eptp);
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bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
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int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
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u64 fault_address, char *insn, int insn_len);
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void __kvm_mmu_refresh_passthrough_bits(struct kvm_vcpu *vcpu,
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struct kvm_mmu *mmu);
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int kvm_mmu_load(struct kvm_vcpu *vcpu);
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void kvm_mmu_unload(struct kvm_vcpu *vcpu);
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void kvm_mmu_free_obsolete_roots(struct kvm_vcpu *vcpu);
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void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
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void kvm_mmu_sync_prev_roots(struct kvm_vcpu *vcpu);
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static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
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{
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if (likely(vcpu->arch.mmu->root.hpa != INVALID_PAGE))
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return 0;
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return kvm_mmu_load(vcpu);
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}
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static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3)
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{
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BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0);
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return kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)
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? cr3 & X86_CR3_PCID_MASK
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: 0;
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}
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static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu)
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{
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return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu));
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}
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static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu)
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{
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u64 root_hpa = vcpu->arch.mmu->root.hpa;
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if (!VALID_PAGE(root_hpa))
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return;
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static_call(kvm_x86_load_mmu_pgd)(vcpu, root_hpa,
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vcpu->arch.mmu->root_role.level);
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}
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static inline void kvm_mmu_refresh_passthrough_bits(struct kvm_vcpu *vcpu,
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struct kvm_mmu *mmu)
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{
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/*
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* When EPT is enabled, KVM may passthrough CR0.WP to the guest, i.e.
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* @mmu's snapshot of CR0.WP and thus all related paging metadata may
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* be stale. Refresh CR0.WP and the metadata on-demand when checking
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* for permission faults. Exempt nested MMUs, i.e. MMUs for shadowing
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* nEPT and nNPT, as CR0.WP is ignored in both cases. Note, KVM does
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* need to refresh nested_mmu, a.k.a. the walker used to translate L2
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* GVAs to GPAs, as that "MMU" needs to honor L2's CR0.WP.
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*/
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if (!tdp_enabled || mmu == &vcpu->arch.guest_mmu)
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return;
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__kvm_mmu_refresh_passthrough_bits(vcpu, mmu);
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}
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/*
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* Check if a given access (described through the I/D, W/R and U/S bits of a
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* page fault error code pfec) causes a permission fault with the given PTE
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* access rights (in ACC_* format).
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*
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* Return zero if the access does not fault; return the page fault error code
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* if the access faults.
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*/
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static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
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unsigned pte_access, unsigned pte_pkey,
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u64 access)
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{
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/* strip nested paging fault error codes */
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unsigned int pfec = access;
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unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
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/*
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* For explicit supervisor accesses, SMAP is disabled if EFLAGS.AC = 1.
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* For implicit supervisor accesses, SMAP cannot be overridden.
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*
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* SMAP works on supervisor accesses only, and not_smap can
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* be set or not set when user access with neither has any bearing
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* on the result.
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*
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* We put the SMAP checking bit in place of the PFERR_RSVD_MASK bit;
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* this bit will always be zero in pfec, but it will be one in index
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* if SMAP checks are being disabled.
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*/
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u64 implicit_access = access & PFERR_IMPLICIT_ACCESS;
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bool not_smap = ((rflags & X86_EFLAGS_AC) | implicit_access) == X86_EFLAGS_AC;
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int index = (pfec + (not_smap << PFERR_RSVD_BIT)) >> 1;
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u32 errcode = PFERR_PRESENT_MASK;
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bool fault;
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kvm_mmu_refresh_passthrough_bits(vcpu, mmu);
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fault = (mmu->permissions[index] >> pte_access) & 1;
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WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
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if (unlikely(mmu->pkru_mask)) {
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u32 pkru_bits, offset;
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/*
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* PKRU defines 32 bits, there are 16 domains and 2
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* attribute bits per domain in pkru. pte_pkey is the
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* index of the protection domain, so pte_pkey * 2 is
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* is the index of the first bit for the domain.
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*/
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pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
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/* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
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offset = (pfec & ~1) +
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((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT));
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pkru_bits &= mmu->pkru_mask >> offset;
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errcode |= -pkru_bits & PFERR_PK_MASK;
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fault |= (pkru_bits != 0);
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}
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return -(u32)fault & errcode;
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}
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void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end);
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int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu);
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int kvm_mmu_post_init_vm(struct kvm *kvm);
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void kvm_mmu_pre_destroy_vm(struct kvm *kvm);
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static inline bool kvm_shadow_root_allocated(struct kvm *kvm)
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{
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/*
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* Read shadow_root_allocated before related pointers. Hence, threads
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* reading shadow_root_allocated in any lock context are guaranteed to
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* see the pointers. Pairs with smp_store_release in
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* mmu_first_shadow_root_alloc.
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*/
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return smp_load_acquire(&kvm->arch.shadow_root_allocated);
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}
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#ifdef CONFIG_X86_64
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extern bool tdp_mmu_enabled;
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#else
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#define tdp_mmu_enabled false
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#endif
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static inline bool kvm_memslots_have_rmaps(struct kvm *kvm)
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{
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return !tdp_mmu_enabled || kvm_shadow_root_allocated(kvm);
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}
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static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
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{
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/* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */
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return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
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(base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
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}
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static inline unsigned long
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__kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, unsigned long npages,
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int level)
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{
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return gfn_to_index(slot->base_gfn + npages - 1,
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slot->base_gfn, level) + 1;
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}
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static inline unsigned long
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kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, int level)
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{
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return __kvm_mmu_slot_lpages(slot, slot->npages, level);
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}
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static inline void kvm_update_page_stats(struct kvm *kvm, int level, int count)
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{
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atomic64_add(count, &kvm->stat.pages[level - 1]);
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}
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gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
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struct x86_exception *exception);
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static inline gpa_t kvm_translate_gpa(struct kvm_vcpu *vcpu,
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struct kvm_mmu *mmu,
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gpa_t gpa, u64 access,
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struct x86_exception *exception)
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{
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if (mmu != &vcpu->arch.nested_mmu)
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return gpa;
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return translate_nested_gpa(vcpu, gpa, access, exception);
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}
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#endif
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