OpenCloudOS-Kernel/drivers/iommu/intel
Nadav Amit 29b3283972 iommu/vt-d: Do not use flush-queue when caching-mode is on
When an Intel IOMMU is virtualized, and a physical device is
passed-through to the VM, changes of the virtual IOMMU need to be
propagated to the physical IOMMU. The hypervisor therefore needs to
monitor PTE mappings in the IOMMU page-tables. Intel specifications
provide "caching-mode" capability that a virtual IOMMU uses to report
that the IOMMU is virtualized and a TLB flush is needed after mapping to
allow the hypervisor to propagate virtual IOMMU mappings to the physical
IOMMU. To the best of my knowledge no real physical IOMMU reports
"caching-mode" as turned on.

Synchronizing the virtual and the physical IOMMU tables is expensive if
the hypervisor is unaware which PTEs have changed, as the hypervisor is
required to walk all the virtualized tables and look for changes.
Consequently, domain flushes are much more expensive than page-specific
flushes on virtualized IOMMUs with passthrough devices. The kernel
therefore exploited the "caching-mode" indication to avoid domain
flushing and use page-specific flushing in virtualized environments. See
commit 78d5f0f500 ("intel-iommu: Avoid global flushes with caching
mode.")

This behavior changed after commit 13cf017446 ("iommu/vt-d: Make use
of iova deferred flushing"). Now, when batched TLB flushing is used (the
default), full TLB domain flushes are performed frequently, requiring
the hypervisor to perform expensive synchronization between the virtual
TLB and the physical one.

Getting batched TLB flushes to use page-specific invalidations again in
such circumstances is not easy, since the TLB invalidation scheme
assumes that "full" domain TLB flushes are performed for scalability.

Disable batched TLB flushes when caching-mode is on, as the performance
benefit from using batched TLB invalidations is likely to be much
smaller than the overhead of the virtual-to-physical IOMMU page-tables
synchronization.

Fixes: 13cf017446 ("iommu/vt-d: Make use of iova deferred flushing")
Signed-off-by: Nadav Amit <namit@vmware.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Lu Baolu <baolu.lu@linux.intel.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Will Deacon <will@kernel.org>
Cc: stable@vger.kernel.org

Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210127175317.1600473-1-namit@vmware.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-01-28 13:59:02 +01:00
..
Kconfig iommu/vt-d: Convert intel iommu driver to the iommu ops 2020-11-25 12:03:49 +00:00
Makefile iommu/vt-d: Move Kconfig and Makefile bits down into intel directory 2020-07-29 14:14:55 +02:00
debugfs.c iommu/vt-d: Rename intel-pasid.h to pasid.h 2020-07-24 10:51:21 +02:00
dmar.c iommu/vt-d: Correctly check addr alignment in qi_flush_dev_iotlb_pasid() 2021-01-28 13:17:08 +01:00
iommu.c iommu/vt-d: Do not use flush-queue when caching-mode is on 2021-01-28 13:59:02 +01:00
irq_remapping.c iommu/intel: Fix memleak in intel_irq_remapping_alloc 2021-01-05 19:12:06 +00:00
pasid.c drm, iommu: Change type of pasid to u32 2020-09-17 19:21:16 +02:00
pasid.h drm, iommu: Change type of pasid to u32 2020-09-17 19:21:16 +02:00
svm.c iommu/vt-d: Fix unaligned addresses for intel_flush_svm_range_dev() 2021-01-12 15:47:54 +00:00
trace.c