464 lines
13 KiB
C
464 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* GPIO driver for the ACCES 104-DIO-48E series
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* Copyright (C) 2016 William Breathitt Gray
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*
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* This driver supports the following ACCES devices: 104-DIO-48E and
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* 104-DIO-24E.
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*/
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/irqdesc.h>
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#include <linux/isa.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#define DIO48E_EXTENT 16
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#define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT)
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static unsigned int base[MAX_NUM_DIO48E];
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static unsigned int num_dio48e;
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module_param_hw_array(base, uint, ioport, &num_dio48e, 0);
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MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
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static unsigned int irq[MAX_NUM_DIO48E];
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module_param_hw_array(irq, uint, irq, NULL, 0);
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MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
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/**
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* struct dio48e_gpio - GPIO device private data structure
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* @chip: instance of the gpio_chip
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* @io_state: bit I/O state (whether bit is set to input or output)
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* @out_state: output bits state
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* @control: Control registers state
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* @lock: synchronization lock to prevent I/O race conditions
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* @base: base port address of the GPIO device
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* @irq_mask: I/O bits affected by interrupts
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*/
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struct dio48e_gpio {
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struct gpio_chip chip;
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unsigned char io_state[6];
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unsigned char out_state[6];
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unsigned char control[2];
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raw_spinlock_t lock;
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unsigned int base;
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unsigned char irq_mask;
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};
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static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned int port = offset / 8;
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const unsigned int mask = BIT(offset % 8);
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if (dio48egpio->io_state[port] & mask)
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned int io_port = offset / 8;
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const unsigned int control_port = io_port / 3;
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const unsigned int control_addr = dio48egpio->base + 3 + control_port * 4;
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unsigned long flags;
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unsigned int control;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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/* Check if configuring Port C */
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if (io_port == 2 || io_port == 5) {
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/* Port C can be configured by nibble */
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if (offset % 8 > 3) {
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dio48egpio->io_state[io_port] |= 0xF0;
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dio48egpio->control[control_port] |= BIT(3);
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} else {
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dio48egpio->io_state[io_port] |= 0x0F;
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dio48egpio->control[control_port] |= BIT(0);
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}
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} else {
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dio48egpio->io_state[io_port] |= 0xFF;
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if (io_port == 0 || io_port == 3)
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dio48egpio->control[control_port] |= BIT(4);
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else
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dio48egpio->control[control_port] |= BIT(1);
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}
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control = BIT(7) | dio48egpio->control[control_port];
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outb(control, control_addr);
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control &= ~BIT(7);
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outb(control, control_addr);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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return 0;
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}
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static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned int io_port = offset / 8;
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const unsigned int control_port = io_port / 3;
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const unsigned int mask = BIT(offset % 8);
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const unsigned int control_addr = dio48egpio->base + 3 + control_port * 4;
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const unsigned int out_port = (io_port > 2) ? io_port + 1 : io_port;
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unsigned long flags;
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unsigned int control;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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/* Check if configuring Port C */
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if (io_port == 2 || io_port == 5) {
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/* Port C can be configured by nibble */
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if (offset % 8 > 3) {
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dio48egpio->io_state[io_port] &= 0x0F;
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dio48egpio->control[control_port] &= ~BIT(3);
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} else {
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dio48egpio->io_state[io_port] &= 0xF0;
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dio48egpio->control[control_port] &= ~BIT(0);
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}
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} else {
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dio48egpio->io_state[io_port] &= 0x00;
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if (io_port == 0 || io_port == 3)
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dio48egpio->control[control_port] &= ~BIT(4);
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else
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dio48egpio->control[control_port] &= ~BIT(1);
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}
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if (value)
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dio48egpio->out_state[io_port] |= mask;
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else
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dio48egpio->out_state[io_port] &= ~mask;
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control = BIT(7) | dio48egpio->control[control_port];
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outb(control, control_addr);
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outb(dio48egpio->out_state[io_port], dio48egpio->base + out_port);
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control &= ~BIT(7);
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outb(control, control_addr);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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return 0;
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}
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static int dio48e_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned int port = offset / 8;
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const unsigned int mask = BIT(offset % 8);
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const unsigned int in_port = (port > 2) ? port + 1 : port;
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unsigned long flags;
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unsigned int port_state;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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/* ensure that GPIO is set for input */
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if (!(dio48egpio->io_state[port] & mask)) {
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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return -EINVAL;
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}
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port_state = inb(dio48egpio->base + in_port);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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return !!(port_state & mask);
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}
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static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
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static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
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unsigned long *bits)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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unsigned int port_addr;
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unsigned long port_state;
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/* clear bits array to a clean slate */
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bitmap_zero(bits, chip->ngpio);
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for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
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port_addr = dio48egpio->base + ports[offset / 8];
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port_state = inb(port_addr) & gpio_mask;
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bitmap_set_value8(bits, port_state, offset);
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}
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return 0;
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}
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static void dio48e_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned int port = offset / 8;
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const unsigned int mask = BIT(offset % 8);
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const unsigned int out_port = (port > 2) ? port + 1 : port;
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unsigned long flags;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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if (value)
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dio48egpio->out_state[port] |= mask;
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else
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dio48egpio->out_state[port] &= ~mask;
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outb(dio48egpio->out_state[port], dio48egpio->base + out_port);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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}
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static void dio48e_gpio_set_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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size_t index;
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unsigned int port_addr;
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unsigned long bitmask;
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unsigned long flags;
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for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
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index = offset / 8;
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port_addr = dio48egpio->base + ports[index];
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bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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/* update output state data and set device gpio register */
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dio48egpio->out_state[index] &= ~gpio_mask;
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dio48egpio->out_state[index] |= bitmask;
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outb(dio48egpio->out_state[index], port_addr);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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}
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}
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static void dio48e_irq_ack(struct irq_data *data)
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{
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}
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static void dio48e_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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unsigned long flags;
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/* only bit 3 on each respective Port C supports interrupts */
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if (offset != 19 && offset != 43)
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return;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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if (offset == 19)
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dio48egpio->irq_mask &= ~BIT(0);
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else
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dio48egpio->irq_mask &= ~BIT(1);
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if (!dio48egpio->irq_mask)
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/* disable interrupts */
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inb(dio48egpio->base + 0xB);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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}
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static void dio48e_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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unsigned long flags;
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/* only bit 3 on each respective Port C supports interrupts */
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if (offset != 19 && offset != 43)
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return;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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if (!dio48egpio->irq_mask) {
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/* enable interrupts */
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outb(0x00, dio48egpio->base + 0xF);
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outb(0x00, dio48egpio->base + 0xB);
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}
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if (offset == 19)
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dio48egpio->irq_mask |= BIT(0);
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else
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dio48egpio->irq_mask |= BIT(1);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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}
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static int dio48e_irq_set_type(struct irq_data *data, unsigned int flow_type)
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{
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const unsigned long offset = irqd_to_hwirq(data);
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/* only bit 3 on each respective Port C supports interrupts */
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if (offset != 19 && offset != 43)
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return -EINVAL;
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if (flow_type != IRQ_TYPE_NONE && flow_type != IRQ_TYPE_EDGE_RISING)
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return -EINVAL;
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return 0;
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}
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static struct irq_chip dio48e_irqchip = {
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.name = "104-dio-48e",
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.irq_ack = dio48e_irq_ack,
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.irq_mask = dio48e_irq_mask,
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.irq_unmask = dio48e_irq_unmask,
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.irq_set_type = dio48e_irq_set_type
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};
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static irqreturn_t dio48e_irq_handler(int irq, void *dev_id)
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{
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struct dio48e_gpio *const dio48egpio = dev_id;
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struct gpio_chip *const chip = &dio48egpio->chip;
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const unsigned long irq_mask = dio48egpio->irq_mask;
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unsigned long gpio;
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for_each_set_bit(gpio, &irq_mask, 2)
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generic_handle_domain_irq(chip->irq.domain,
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19 + gpio*24);
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raw_spin_lock(&dio48egpio->lock);
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outb(0x00, dio48egpio->base + 0xF);
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raw_spin_unlock(&dio48egpio->lock);
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return IRQ_HANDLED;
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}
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#define DIO48E_NGPIO 48
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static const char *dio48e_names[DIO48E_NGPIO] = {
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"PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2",
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"PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5",
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"PPI Group 0 Port A 6", "PPI Group 0 Port A 7", "PPI Group 0 Port B 0",
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"PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3",
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"PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6",
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"PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1",
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"PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4",
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"PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7",
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"PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2",
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"PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5",
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"PPI Group 1 Port A 6", "PPI Group 1 Port A 7", "PPI Group 1 Port B 0",
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"PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3",
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"PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6",
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"PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1",
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"PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4",
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"PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7"
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};
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static int dio48e_irq_init_hw(struct gpio_chip *gc)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(gc);
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/* Disable IRQ by default */
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inb(dio48egpio->base + 0xB);
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return 0;
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}
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static int dio48e_probe(struct device *dev, unsigned int id)
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{
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struct dio48e_gpio *dio48egpio;
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const char *const name = dev_name(dev);
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struct gpio_irq_chip *girq;
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int err;
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dio48egpio = devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL);
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if (!dio48egpio)
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return -ENOMEM;
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if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) {
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dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
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base[id], base[id] + DIO48E_EXTENT);
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return -EBUSY;
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}
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dio48egpio->chip.label = name;
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dio48egpio->chip.parent = dev;
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dio48egpio->chip.owner = THIS_MODULE;
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dio48egpio->chip.base = -1;
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dio48egpio->chip.ngpio = DIO48E_NGPIO;
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dio48egpio->chip.names = dio48e_names;
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dio48egpio->chip.get_direction = dio48e_gpio_get_direction;
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dio48egpio->chip.direction_input = dio48e_gpio_direction_input;
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dio48egpio->chip.direction_output = dio48e_gpio_direction_output;
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dio48egpio->chip.get = dio48e_gpio_get;
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dio48egpio->chip.get_multiple = dio48e_gpio_get_multiple;
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dio48egpio->chip.set = dio48e_gpio_set;
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dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple;
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dio48egpio->base = base[id];
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girq = &dio48egpio->chip.irq;
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girq->chip = &dio48e_irqchip;
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/* This will let us handle the parent IRQ in the driver */
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girq->parent_handler = NULL;
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girq->num_parents = 0;
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girq->parents = NULL;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_edge_irq;
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girq->init_hw = dio48e_irq_init_hw;
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raw_spin_lock_init(&dio48egpio->lock);
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/* initialize all GPIO as output */
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outb(0x80, base[id] + 3);
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outb(0x00, base[id]);
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outb(0x00, base[id] + 1);
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outb(0x00, base[id] + 2);
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outb(0x00, base[id] + 3);
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outb(0x80, base[id] + 7);
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outb(0x00, base[id] + 4);
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outb(0x00, base[id] + 5);
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outb(0x00, base[id] + 6);
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outb(0x00, base[id] + 7);
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err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio);
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if (err) {
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dev_err(dev, "GPIO registering failed (%d)\n", err);
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return err;
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}
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err = devm_request_irq(dev, irq[id], dio48e_irq_handler, 0, name,
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dio48egpio);
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if (err) {
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dev_err(dev, "IRQ handler registering failed (%d)\n", err);
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return err;
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}
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return 0;
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}
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static struct isa_driver dio48e_driver = {
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.probe = dio48e_probe,
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.driver = {
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.name = "104-dio-48e"
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},
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|
};
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module_isa_driver(dio48e_driver, num_dio48e);
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MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
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MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver");
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MODULE_LICENSE("GPL v2");
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