115 lines
3.3 KiB
C
115 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _LINUX_DMA_NONCOHERENT_H
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#define _LINUX_DMA_NONCOHERENT_H 1
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#include <linux/dma-mapping.h>
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#include <asm/pgtable.h>
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#ifdef CONFIG_ARCH_HAS_DMA_COHERENCE_H
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#include <asm/dma-coherence.h>
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#elif defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
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defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
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defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
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static inline bool dev_is_dma_coherent(struct device *dev)
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{
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return dev->dma_coherent;
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}
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#else
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static inline bool dev_is_dma_coherent(struct device *dev)
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{
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return true;
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}
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#endif /* CONFIG_ARCH_HAS_DMA_COHERENCE_H */
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/*
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* Check if an allocation needs to be marked uncached to be coherent.
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*/
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static __always_inline bool dma_alloc_need_uncached(struct device *dev,
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unsigned long attrs)
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{
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if (dev_is_dma_coherent(dev))
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return false;
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if (attrs & DMA_ATTR_NO_KERNEL_MAPPING)
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return false;
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if (IS_ENABLED(CONFIG_DMA_NONCOHERENT_CACHE_SYNC) &&
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(attrs & DMA_ATTR_NON_CONSISTENT))
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return false;
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return true;
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}
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void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
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gfp_t gfp, unsigned long attrs);
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void arch_dma_free(struct device *dev, size_t size, void *cpu_addr,
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dma_addr_t dma_addr, unsigned long attrs);
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#ifdef CONFIG_MMU
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/*
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* Page protection so that devices that can't snoop CPU caches can use the
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* memory coherently. We default to pgprot_noncached which is usually used
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* for ioremap as a safe bet, but architectures can override this with less
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* strict semantics if possible.
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*/
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#ifndef pgprot_dmacoherent
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#define pgprot_dmacoherent(prot) pgprot_noncached(prot)
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#endif
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pgprot_t dma_pgprot(struct device *dev, pgprot_t prot, unsigned long attrs);
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#else
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static inline pgprot_t dma_pgprot(struct device *dev, pgprot_t prot,
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unsigned long attrs)
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{
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return prot; /* no protection bits supported without page tables */
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}
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#endif /* CONFIG_MMU */
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#ifdef CONFIG_DMA_NONCOHERENT_CACHE_SYNC
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void arch_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction);
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#else
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static inline void arch_dma_cache_sync(struct device *dev, void *vaddr,
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size_t size, enum dma_data_direction direction)
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{
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}
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#endif /* CONFIG_DMA_NONCOHERENT_CACHE_SYNC */
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#ifdef CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE
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void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir);
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#else
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static inline void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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}
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#endif /* ARCH_HAS_SYNC_DMA_FOR_DEVICE */
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#ifdef CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU
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void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir);
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#else
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static inline void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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}
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#endif /* ARCH_HAS_SYNC_DMA_FOR_CPU */
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#ifdef CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
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void arch_sync_dma_for_cpu_all(void);
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#else
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static inline void arch_sync_dma_for_cpu_all(void)
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{
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}
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#endif /* CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL */
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#ifdef CONFIG_ARCH_HAS_DMA_PREP_COHERENT
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void arch_dma_prep_coherent(struct page *page, size_t size);
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#else
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static inline void arch_dma_prep_coherent(struct page *page, size_t size)
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{
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}
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#endif /* CONFIG_ARCH_HAS_DMA_PREP_COHERENT */
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void *arch_dma_set_uncached(void *addr, size_t size);
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void arch_dma_clear_uncached(void *addr, size_t size);
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#endif /* _LINUX_DMA_NONCOHERENT_H */
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