4005 lines
143 KiB
C
4005 lines
143 KiB
C
#ifndef A4XX_XML
|
|
#define A4XX_XML
|
|
|
|
/* Autogenerated file, DO NOT EDIT manually!
|
|
|
|
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
|
http://github.com/freedreno/envytools/
|
|
git clone https://github.com/freedreno/envytools.git
|
|
|
|
The rules-ng-ng source files this header was generated from are:
|
|
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
|
|
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
|
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
|
|
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
|
|
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
|
|
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
|
|
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48)
|
|
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
|
|
|
|
Copyright (C) 2013-2016 by the following authors:
|
|
- Rob Clark <robdclark@gmail.com> (robclark)
|
|
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
|
|
|
Permission is hereby granted, free of charge, to any person obtaining
|
|
a copy of this software and associated documentation files (the
|
|
"Software"), to deal in the Software without restriction, including
|
|
without limitation the rights to use, copy, modify, merge, publish,
|
|
distribute, sublicense, and/or sell copies of the Software, and to
|
|
permit persons to whom the Software is furnished to do so, subject to
|
|
the following conditions:
|
|
|
|
The above copyright notice and this permission notice (including the
|
|
next paragraph) shall be included in all copies or substantial
|
|
portions of the Software.
|
|
|
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
|
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
|
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
|
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
|
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
|
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
|
|
enum a4xx_color_fmt {
|
|
RB4_A8_UNORM = 1,
|
|
RB4_R8_UNORM = 2,
|
|
RB4_R4G4B4A4_UNORM = 8,
|
|
RB4_R5G5B5A1_UNORM = 10,
|
|
RB4_R5G6B5_UNORM = 14,
|
|
RB4_R8G8_UNORM = 15,
|
|
RB4_R8G8_SNORM = 16,
|
|
RB4_R8G8_UINT = 17,
|
|
RB4_R8G8_SINT = 18,
|
|
RB4_R16_UNORM = 19,
|
|
RB4_R16_SNORM = 20,
|
|
RB4_R16_FLOAT = 21,
|
|
RB4_R16_UINT = 22,
|
|
RB4_R16_SINT = 23,
|
|
RB4_R8G8B8_UNORM = 25,
|
|
RB4_R8G8B8A8_UNORM = 26,
|
|
RB4_R8G8B8A8_SNORM = 28,
|
|
RB4_R8G8B8A8_UINT = 29,
|
|
RB4_R8G8B8A8_SINT = 30,
|
|
RB4_R10G10B10A2_UNORM = 31,
|
|
RB4_R10G10B10A2_UINT = 34,
|
|
RB4_R11G11B10_FLOAT = 39,
|
|
RB4_R16G16_UNORM = 40,
|
|
RB4_R16G16_SNORM = 41,
|
|
RB4_R16G16_FLOAT = 42,
|
|
RB4_R16G16_UINT = 43,
|
|
RB4_R16G16_SINT = 44,
|
|
RB4_R32_FLOAT = 45,
|
|
RB4_R32_UINT = 46,
|
|
RB4_R32_SINT = 47,
|
|
RB4_R16G16B16A16_UNORM = 52,
|
|
RB4_R16G16B16A16_SNORM = 53,
|
|
RB4_R16G16B16A16_FLOAT = 54,
|
|
RB4_R16G16B16A16_UINT = 55,
|
|
RB4_R16G16B16A16_SINT = 56,
|
|
RB4_R32G32_FLOAT = 57,
|
|
RB4_R32G32_UINT = 58,
|
|
RB4_R32G32_SINT = 59,
|
|
RB4_R32G32B32A32_FLOAT = 60,
|
|
RB4_R32G32B32A32_UINT = 61,
|
|
RB4_R32G32B32A32_SINT = 62,
|
|
};
|
|
|
|
enum a4xx_tile_mode {
|
|
TILE4_LINEAR = 0,
|
|
TILE4_3 = 3,
|
|
};
|
|
|
|
enum a4xx_rb_blend_opcode {
|
|
BLEND_DST_PLUS_SRC = 0,
|
|
BLEND_SRC_MINUS_DST = 1,
|
|
BLEND_DST_MINUS_SRC = 2,
|
|
BLEND_MIN_DST_SRC = 3,
|
|
BLEND_MAX_DST_SRC = 4,
|
|
};
|
|
|
|
enum a4xx_vtx_fmt {
|
|
VFMT4_32_FLOAT = 1,
|
|
VFMT4_32_32_FLOAT = 2,
|
|
VFMT4_32_32_32_FLOAT = 3,
|
|
VFMT4_32_32_32_32_FLOAT = 4,
|
|
VFMT4_16_FLOAT = 5,
|
|
VFMT4_16_16_FLOAT = 6,
|
|
VFMT4_16_16_16_FLOAT = 7,
|
|
VFMT4_16_16_16_16_FLOAT = 8,
|
|
VFMT4_32_FIXED = 9,
|
|
VFMT4_32_32_FIXED = 10,
|
|
VFMT4_32_32_32_FIXED = 11,
|
|
VFMT4_32_32_32_32_FIXED = 12,
|
|
VFMT4_11_11_10_FLOAT = 13,
|
|
VFMT4_16_SINT = 16,
|
|
VFMT4_16_16_SINT = 17,
|
|
VFMT4_16_16_16_SINT = 18,
|
|
VFMT4_16_16_16_16_SINT = 19,
|
|
VFMT4_16_UINT = 20,
|
|
VFMT4_16_16_UINT = 21,
|
|
VFMT4_16_16_16_UINT = 22,
|
|
VFMT4_16_16_16_16_UINT = 23,
|
|
VFMT4_16_SNORM = 24,
|
|
VFMT4_16_16_SNORM = 25,
|
|
VFMT4_16_16_16_SNORM = 26,
|
|
VFMT4_16_16_16_16_SNORM = 27,
|
|
VFMT4_16_UNORM = 28,
|
|
VFMT4_16_16_UNORM = 29,
|
|
VFMT4_16_16_16_UNORM = 30,
|
|
VFMT4_16_16_16_16_UNORM = 31,
|
|
VFMT4_32_UINT = 32,
|
|
VFMT4_32_32_UINT = 33,
|
|
VFMT4_32_32_32_UINT = 34,
|
|
VFMT4_32_32_32_32_UINT = 35,
|
|
VFMT4_32_SINT = 36,
|
|
VFMT4_32_32_SINT = 37,
|
|
VFMT4_32_32_32_SINT = 38,
|
|
VFMT4_32_32_32_32_SINT = 39,
|
|
VFMT4_8_UINT = 40,
|
|
VFMT4_8_8_UINT = 41,
|
|
VFMT4_8_8_8_UINT = 42,
|
|
VFMT4_8_8_8_8_UINT = 43,
|
|
VFMT4_8_UNORM = 44,
|
|
VFMT4_8_8_UNORM = 45,
|
|
VFMT4_8_8_8_UNORM = 46,
|
|
VFMT4_8_8_8_8_UNORM = 47,
|
|
VFMT4_8_SINT = 48,
|
|
VFMT4_8_8_SINT = 49,
|
|
VFMT4_8_8_8_SINT = 50,
|
|
VFMT4_8_8_8_8_SINT = 51,
|
|
VFMT4_8_SNORM = 52,
|
|
VFMT4_8_8_SNORM = 53,
|
|
VFMT4_8_8_8_SNORM = 54,
|
|
VFMT4_8_8_8_8_SNORM = 55,
|
|
VFMT4_10_10_10_2_UINT = 56,
|
|
VFMT4_10_10_10_2_UNORM = 57,
|
|
VFMT4_10_10_10_2_SINT = 58,
|
|
VFMT4_10_10_10_2_SNORM = 59,
|
|
VFMT4_2_10_10_10_UINT = 60,
|
|
VFMT4_2_10_10_10_UNORM = 61,
|
|
VFMT4_2_10_10_10_SINT = 62,
|
|
VFMT4_2_10_10_10_SNORM = 63,
|
|
};
|
|
|
|
enum a4xx_tex_fmt {
|
|
TFMT4_A8_UNORM = 3,
|
|
TFMT4_8_UNORM = 4,
|
|
TFMT4_8_SNORM = 5,
|
|
TFMT4_8_UINT = 6,
|
|
TFMT4_8_SINT = 7,
|
|
TFMT4_4_4_4_4_UNORM = 8,
|
|
TFMT4_5_5_5_1_UNORM = 9,
|
|
TFMT4_5_6_5_UNORM = 11,
|
|
TFMT4_L8_A8_UNORM = 13,
|
|
TFMT4_8_8_UNORM = 14,
|
|
TFMT4_8_8_SNORM = 15,
|
|
TFMT4_8_8_UINT = 16,
|
|
TFMT4_8_8_SINT = 17,
|
|
TFMT4_16_UNORM = 18,
|
|
TFMT4_16_SNORM = 19,
|
|
TFMT4_16_FLOAT = 20,
|
|
TFMT4_16_UINT = 21,
|
|
TFMT4_16_SINT = 22,
|
|
TFMT4_8_8_8_8_UNORM = 28,
|
|
TFMT4_8_8_8_8_SNORM = 29,
|
|
TFMT4_8_8_8_8_UINT = 30,
|
|
TFMT4_8_8_8_8_SINT = 31,
|
|
TFMT4_9_9_9_E5_FLOAT = 32,
|
|
TFMT4_10_10_10_2_UNORM = 33,
|
|
TFMT4_10_10_10_2_UINT = 34,
|
|
TFMT4_11_11_10_FLOAT = 37,
|
|
TFMT4_16_16_UNORM = 38,
|
|
TFMT4_16_16_SNORM = 39,
|
|
TFMT4_16_16_FLOAT = 40,
|
|
TFMT4_16_16_UINT = 41,
|
|
TFMT4_16_16_SINT = 42,
|
|
TFMT4_32_FLOAT = 43,
|
|
TFMT4_32_UINT = 44,
|
|
TFMT4_32_SINT = 45,
|
|
TFMT4_16_16_16_16_UNORM = 51,
|
|
TFMT4_16_16_16_16_SNORM = 52,
|
|
TFMT4_16_16_16_16_FLOAT = 53,
|
|
TFMT4_16_16_16_16_UINT = 54,
|
|
TFMT4_16_16_16_16_SINT = 55,
|
|
TFMT4_32_32_FLOAT = 56,
|
|
TFMT4_32_32_UINT = 57,
|
|
TFMT4_32_32_SINT = 58,
|
|
TFMT4_32_32_32_FLOAT = 59,
|
|
TFMT4_32_32_32_UINT = 60,
|
|
TFMT4_32_32_32_SINT = 61,
|
|
TFMT4_32_32_32_32_FLOAT = 63,
|
|
TFMT4_32_32_32_32_UINT = 64,
|
|
TFMT4_32_32_32_32_SINT = 65,
|
|
TFMT4_X8Z24_UNORM = 71,
|
|
TFMT4_DXT1 = 86,
|
|
TFMT4_DXT3 = 87,
|
|
TFMT4_DXT5 = 88,
|
|
TFMT4_RGTC1_UNORM = 90,
|
|
TFMT4_RGTC1_SNORM = 91,
|
|
TFMT4_RGTC2_UNORM = 94,
|
|
TFMT4_RGTC2_SNORM = 95,
|
|
TFMT4_BPTC_UFLOAT = 97,
|
|
TFMT4_BPTC_FLOAT = 98,
|
|
TFMT4_BPTC = 99,
|
|
TFMT4_ATC_RGB = 100,
|
|
TFMT4_ATC_RGBA_EXPLICIT = 101,
|
|
TFMT4_ATC_RGBA_INTERPOLATED = 102,
|
|
TFMT4_ETC2_RG11_UNORM = 103,
|
|
TFMT4_ETC2_RG11_SNORM = 104,
|
|
TFMT4_ETC2_R11_UNORM = 105,
|
|
TFMT4_ETC2_R11_SNORM = 106,
|
|
TFMT4_ETC1 = 107,
|
|
TFMT4_ETC2_RGB8 = 108,
|
|
TFMT4_ETC2_RGBA8 = 109,
|
|
TFMT4_ETC2_RGB8A1 = 110,
|
|
TFMT4_ASTC_4x4 = 111,
|
|
TFMT4_ASTC_5x4 = 112,
|
|
TFMT4_ASTC_5x5 = 113,
|
|
TFMT4_ASTC_6x5 = 114,
|
|
TFMT4_ASTC_6x6 = 115,
|
|
TFMT4_ASTC_8x5 = 116,
|
|
TFMT4_ASTC_8x6 = 117,
|
|
TFMT4_ASTC_8x8 = 118,
|
|
TFMT4_ASTC_10x5 = 119,
|
|
TFMT4_ASTC_10x6 = 120,
|
|
TFMT4_ASTC_10x8 = 121,
|
|
TFMT4_ASTC_10x10 = 122,
|
|
TFMT4_ASTC_12x10 = 123,
|
|
TFMT4_ASTC_12x12 = 124,
|
|
};
|
|
|
|
enum a4xx_tex_fetchsize {
|
|
TFETCH4_1_BYTE = 0,
|
|
TFETCH4_2_BYTE = 1,
|
|
TFETCH4_4_BYTE = 2,
|
|
TFETCH4_8_BYTE = 3,
|
|
TFETCH4_16_BYTE = 4,
|
|
};
|
|
|
|
enum a4xx_depth_format {
|
|
DEPTH4_NONE = 0,
|
|
DEPTH4_16 = 1,
|
|
DEPTH4_24_8 = 2,
|
|
DEPTH4_32 = 3,
|
|
};
|
|
|
|
enum a4xx_tess_spacing {
|
|
EQUAL_SPACING = 0,
|
|
ODD_SPACING = 2,
|
|
EVEN_SPACING = 3,
|
|
};
|
|
|
|
enum a4xx_ccu_perfcounter_select {
|
|
CCU_BUSY_CYCLES = 0,
|
|
CCU_RB_DEPTH_RETURN_STALL = 2,
|
|
CCU_RB_COLOR_RETURN_STALL = 3,
|
|
CCU_DEPTH_BLOCKS = 6,
|
|
CCU_COLOR_BLOCKS = 7,
|
|
CCU_DEPTH_BLOCK_HIT = 8,
|
|
CCU_COLOR_BLOCK_HIT = 9,
|
|
CCU_DEPTH_FLAG1_COUNT = 10,
|
|
CCU_DEPTH_FLAG2_COUNT = 11,
|
|
CCU_DEPTH_FLAG3_COUNT = 12,
|
|
CCU_DEPTH_FLAG4_COUNT = 13,
|
|
CCU_COLOR_FLAG1_COUNT = 14,
|
|
CCU_COLOR_FLAG2_COUNT = 15,
|
|
CCU_COLOR_FLAG3_COUNT = 16,
|
|
CCU_COLOR_FLAG4_COUNT = 17,
|
|
CCU_PARTIAL_BLOCK_READ = 18,
|
|
};
|
|
|
|
enum a4xx_cp_perfcounter_select {
|
|
CP_ALWAYS_COUNT = 0,
|
|
CP_BUSY = 1,
|
|
CP_PFP_IDLE = 2,
|
|
CP_PFP_BUSY_WORKING = 3,
|
|
CP_PFP_STALL_CYCLES_ANY = 4,
|
|
CP_PFP_STARVE_CYCLES_ANY = 5,
|
|
CP_PFP_STARVED_PER_LOAD_ADDR = 6,
|
|
CP_PFP_STALLED_PER_STORE_ADDR = 7,
|
|
CP_PFP_PC_PROFILE = 8,
|
|
CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
|
|
CP_PFP_COND_INDIRECT_DISCARDED = 10,
|
|
CP_LONG_RESUMPTIONS = 11,
|
|
CP_RESUME_CYCLES = 12,
|
|
CP_RESUME_TO_BOUNDARY_CYCLES = 13,
|
|
CP_LONG_PREEMPTIONS = 14,
|
|
CP_PREEMPT_CYCLES = 15,
|
|
CP_PREEMPT_TO_BOUNDARY_CYCLES = 16,
|
|
CP_ME_FIFO_EMPTY_PFP_IDLE = 17,
|
|
CP_ME_FIFO_EMPTY_PFP_BUSY = 18,
|
|
CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19,
|
|
CP_ME_FIFO_FULL_ME_BUSY = 20,
|
|
CP_ME_FIFO_FULL_ME_NON_WORKING = 21,
|
|
CP_ME_WAITING_FOR_PACKETS = 22,
|
|
CP_ME_BUSY_WORKING = 23,
|
|
CP_ME_STARVE_CYCLES_ANY = 24,
|
|
CP_ME_STARVE_CYCLES_PER_PROFILE = 25,
|
|
CP_ME_STALL_CYCLES_PER_PROFILE = 26,
|
|
CP_ME_PC_PROFILE = 27,
|
|
CP_RCIU_FIFO_EMPTY = 28,
|
|
CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29,
|
|
CP_RCIU_FIFO_FULL = 30,
|
|
CP_RCIU_FIFO_FULL_NO_CONTEXT = 31,
|
|
CP_RCIU_FIFO_FULL_AHB_MASTER = 32,
|
|
CP_RCIU_FIFO_FULL_OTHER = 33,
|
|
CP_AHB_IDLE = 34,
|
|
CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35,
|
|
CP_AHB_STALL_ON_GRANT_SPLIT = 36,
|
|
CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37,
|
|
CP_AHB_BUSY_WORKING = 38,
|
|
CP_AHB_BUSY_STALL_ON_HRDY = 39,
|
|
CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40,
|
|
};
|
|
|
|
enum a4xx_gras_ras_perfcounter_select {
|
|
RAS_SUPER_TILES = 0,
|
|
RAS_8X8_TILES = 1,
|
|
RAS_4X4_TILES = 2,
|
|
RAS_BUSY_CYCLES = 3,
|
|
RAS_STALL_CYCLES_BY_RB = 4,
|
|
RAS_STALL_CYCLES_BY_VSC = 5,
|
|
RAS_STARVE_CYCLES_BY_TSE = 6,
|
|
RAS_SUPERTILE_CYCLES = 7,
|
|
RAS_TILE_CYCLES = 8,
|
|
RAS_FULLY_COVERED_SUPER_TILES = 9,
|
|
RAS_FULLY_COVERED_8X8_TILES = 10,
|
|
RAS_4X4_PRIM = 11,
|
|
RAS_8X4_4X8_PRIM = 12,
|
|
RAS_8X8_PRIM = 13,
|
|
};
|
|
|
|
enum a4xx_gras_tse_perfcounter_select {
|
|
TSE_INPUT_PRIM = 0,
|
|
TSE_INPUT_NULL_PRIM = 1,
|
|
TSE_TRIVAL_REJ_PRIM = 2,
|
|
TSE_CLIPPED_PRIM = 3,
|
|
TSE_NEW_PRIM = 4,
|
|
TSE_ZERO_AREA_PRIM = 5,
|
|
TSE_FACENESS_CULLED_PRIM = 6,
|
|
TSE_ZERO_PIXEL_PRIM = 7,
|
|
TSE_OUTPUT_NULL_PRIM = 8,
|
|
TSE_OUTPUT_VISIBLE_PRIM = 9,
|
|
TSE_PRE_CLIP_PRIM = 10,
|
|
TSE_POST_CLIP_PRIM = 11,
|
|
TSE_BUSY_CYCLES = 12,
|
|
TSE_PC_STARVE = 13,
|
|
TSE_RAS_STALL = 14,
|
|
TSE_STALL_BARYPLANE_FIFO_FULL = 15,
|
|
TSE_STALL_ZPLANE_FIFO_FULL = 16,
|
|
};
|
|
|
|
enum a4xx_hlsq_perfcounter_select {
|
|
HLSQ_SP_VS_STAGE_CONSTANT = 0,
|
|
HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1,
|
|
HLSQ_SP_FS_STAGE_CONSTANT = 2,
|
|
HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3,
|
|
HLSQ_TP_STATE = 4,
|
|
HLSQ_QUADS = 5,
|
|
HLSQ_PIXELS = 6,
|
|
HLSQ_VERTICES = 7,
|
|
HLSQ_SP_VS_STAGE_DATA_BYTES = 13,
|
|
HLSQ_SP_FS_STAGE_DATA_BYTES = 14,
|
|
HLSQ_BUSY_CYCLES = 15,
|
|
HLSQ_STALL_CYCLES_SP_STATE = 16,
|
|
HLSQ_STALL_CYCLES_SP_VS_STAGE = 17,
|
|
HLSQ_STALL_CYCLES_SP_FS_STAGE = 18,
|
|
HLSQ_STALL_CYCLES_UCHE = 19,
|
|
HLSQ_RBBM_LOAD_CYCLES = 20,
|
|
HLSQ_DI_TO_VS_START_SP = 21,
|
|
HLSQ_DI_TO_FS_START_SP = 22,
|
|
HLSQ_VS_STAGE_START_TO_DONE_SP = 23,
|
|
HLSQ_FS_STAGE_START_TO_DONE_SP = 24,
|
|
HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25,
|
|
HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26,
|
|
HLSQ_UCHE_LATENCY_CYCLES = 27,
|
|
HLSQ_UCHE_LATENCY_COUNT = 28,
|
|
HLSQ_STARVE_CYCLES_VFD = 29,
|
|
};
|
|
|
|
enum a4xx_pc_perfcounter_select {
|
|
PC_VIS_STREAMS_LOADED = 0,
|
|
PC_VPC_PRIMITIVES = 2,
|
|
PC_DEAD_PRIM = 3,
|
|
PC_LIVE_PRIM = 4,
|
|
PC_DEAD_DRAWCALLS = 5,
|
|
PC_LIVE_DRAWCALLS = 6,
|
|
PC_VERTEX_MISSES = 7,
|
|
PC_STALL_CYCLES_VFD = 9,
|
|
PC_STALL_CYCLES_TSE = 10,
|
|
PC_STALL_CYCLES_UCHE = 11,
|
|
PC_WORKING_CYCLES = 12,
|
|
PC_IA_VERTICES = 13,
|
|
PC_GS_PRIMITIVES = 14,
|
|
PC_HS_INVOCATIONS = 15,
|
|
PC_DS_INVOCATIONS = 16,
|
|
PC_DS_PRIMITIVES = 17,
|
|
PC_STARVE_CYCLES_FOR_INDEX = 20,
|
|
PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21,
|
|
PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22,
|
|
PC_STALL_CYCLES_TESS = 23,
|
|
PC_STARVE_CYCLES_FOR_POSITION = 24,
|
|
PC_MODE0_DRAWCALL = 25,
|
|
PC_MODE1_DRAWCALL = 26,
|
|
PC_MODE2_DRAWCALL = 27,
|
|
PC_MODE3_DRAWCALL = 28,
|
|
PC_MODE4_DRAWCALL = 29,
|
|
PC_PREDICATED_DEAD_DRAWCALL = 30,
|
|
PC_STALL_CYCLES_BY_TSE_ONLY = 31,
|
|
PC_STALL_CYCLES_BY_VPC_ONLY = 32,
|
|
PC_VPC_POS_DATA_TRANSACTION = 33,
|
|
PC_BUSY_CYCLES = 34,
|
|
PC_STARVE_CYCLES_DI = 35,
|
|
PC_STALL_CYCLES_VPC = 36,
|
|
TESS_WORKING_CYCLES = 37,
|
|
TESS_NUM_CYCLES_SETUP_WORKING = 38,
|
|
TESS_NUM_CYCLES_PTGEN_WORKING = 39,
|
|
TESS_NUM_CYCLES_CONNGEN_WORKING = 40,
|
|
TESS_BUSY_CYCLES = 41,
|
|
TESS_STARVE_CYCLES_PC = 42,
|
|
TESS_STALL_CYCLES_PC = 43,
|
|
};
|
|
|
|
enum a4xx_pwr_perfcounter_select {
|
|
PWR_CORE_CLOCK_CYCLES = 0,
|
|
PWR_BUSY_CLOCK_CYCLES = 1,
|
|
};
|
|
|
|
enum a4xx_rb_perfcounter_select {
|
|
RB_BUSY_CYCLES = 0,
|
|
RB_BUSY_CYCLES_BINNING = 1,
|
|
RB_BUSY_CYCLES_RENDERING = 2,
|
|
RB_BUSY_CYCLES_RESOLVE = 3,
|
|
RB_STARVE_CYCLES_BY_SP = 4,
|
|
RB_STARVE_CYCLES_BY_RAS = 5,
|
|
RB_STARVE_CYCLES_BY_MARB = 6,
|
|
RB_STALL_CYCLES_BY_MARB = 7,
|
|
RB_STALL_CYCLES_BY_HLSQ = 8,
|
|
RB_RB_RB_MARB_DATA = 9,
|
|
RB_SP_RB_QUAD = 10,
|
|
RB_RAS_RB_Z_QUADS = 11,
|
|
RB_GMEM_CH0_READ = 12,
|
|
RB_GMEM_CH1_READ = 13,
|
|
RB_GMEM_CH0_WRITE = 14,
|
|
RB_GMEM_CH1_WRITE = 15,
|
|
RB_CP_CONTEXT_DONE = 16,
|
|
RB_CP_CACHE_FLUSH = 17,
|
|
RB_CP_ZPASS_DONE = 18,
|
|
RB_STALL_FIFO0_FULL = 19,
|
|
RB_STALL_FIFO1_FULL = 20,
|
|
RB_STALL_FIFO2_FULL = 21,
|
|
RB_STALL_FIFO3_FULL = 22,
|
|
RB_RB_HLSQ_TRANSACTIONS = 23,
|
|
RB_Z_READ = 24,
|
|
RB_Z_WRITE = 25,
|
|
RB_C_READ = 26,
|
|
RB_C_WRITE = 27,
|
|
RB_C_READ_LATENCY = 28,
|
|
RB_Z_READ_LATENCY = 29,
|
|
RB_STALL_BY_UCHE = 30,
|
|
RB_MARB_UCHE_TRANSACTIONS = 31,
|
|
RB_CACHE_STALL_MISS = 32,
|
|
RB_CACHE_STALL_FIFO_FULL = 33,
|
|
RB_8BIT_BLENDER_UNITS_ACTIVE = 34,
|
|
RB_16BIT_BLENDER_UNITS_ACTIVE = 35,
|
|
RB_SAMPLER_UNITS_ACTIVE = 36,
|
|
RB_TOTAL_PASS = 38,
|
|
RB_Z_PASS = 39,
|
|
RB_Z_FAIL = 40,
|
|
RB_S_FAIL = 41,
|
|
RB_POWER0 = 42,
|
|
RB_POWER1 = 43,
|
|
RB_POWER2 = 44,
|
|
RB_POWER3 = 45,
|
|
RB_POWER4 = 46,
|
|
RB_POWER5 = 47,
|
|
RB_POWER6 = 48,
|
|
RB_POWER7 = 49,
|
|
};
|
|
|
|
enum a4xx_rbbm_perfcounter_select {
|
|
RBBM_ALWAYS_ON = 0,
|
|
RBBM_VBIF_BUSY = 1,
|
|
RBBM_TSE_BUSY = 2,
|
|
RBBM_RAS_BUSY = 3,
|
|
RBBM_PC_DCALL_BUSY = 4,
|
|
RBBM_PC_VSD_BUSY = 5,
|
|
RBBM_VFD_BUSY = 6,
|
|
RBBM_VPC_BUSY = 7,
|
|
RBBM_UCHE_BUSY = 8,
|
|
RBBM_VSC_BUSY = 9,
|
|
RBBM_HLSQ_BUSY = 10,
|
|
RBBM_ANY_RB_BUSY = 11,
|
|
RBBM_ANY_TPL1_BUSY = 12,
|
|
RBBM_ANY_SP_BUSY = 13,
|
|
RBBM_ANY_MARB_BUSY = 14,
|
|
RBBM_ANY_ARB_BUSY = 15,
|
|
RBBM_AHB_STATUS_BUSY = 16,
|
|
RBBM_AHB_STATUS_STALLED = 17,
|
|
RBBM_AHB_STATUS_TXFR = 18,
|
|
RBBM_AHB_STATUS_TXFR_SPLIT = 19,
|
|
RBBM_AHB_STATUS_TXFR_ERROR = 20,
|
|
RBBM_AHB_STATUS_LONG_STALL = 21,
|
|
RBBM_STATUS_MASKED = 22,
|
|
RBBM_CP_BUSY_GFX_CORE_IDLE = 23,
|
|
RBBM_TESS_BUSY = 24,
|
|
RBBM_COM_BUSY = 25,
|
|
RBBM_DCOM_BUSY = 32,
|
|
RBBM_ANY_CCU_BUSY = 33,
|
|
RBBM_DPM_BUSY = 34,
|
|
};
|
|
|
|
enum a4xx_sp_perfcounter_select {
|
|
SP_LM_LOAD_INSTRUCTIONS = 0,
|
|
SP_LM_STORE_INSTRUCTIONS = 1,
|
|
SP_LM_ATOMICS = 2,
|
|
SP_GM_LOAD_INSTRUCTIONS = 3,
|
|
SP_GM_STORE_INSTRUCTIONS = 4,
|
|
SP_GM_ATOMICS = 5,
|
|
SP_VS_STAGE_TEX_INSTRUCTIONS = 6,
|
|
SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7,
|
|
SP_VS_STAGE_EFU_INSTRUCTIONS = 8,
|
|
SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9,
|
|
SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10,
|
|
SP_FS_STAGE_TEX_INSTRUCTIONS = 11,
|
|
SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12,
|
|
SP_FS_STAGE_EFU_INSTRUCTIONS = 13,
|
|
SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14,
|
|
SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15,
|
|
SP_VS_INSTRUCTIONS = 17,
|
|
SP_FS_INSTRUCTIONS = 18,
|
|
SP_ADDR_LOCK_COUNT = 19,
|
|
SP_UCHE_READ_TRANS = 20,
|
|
SP_UCHE_WRITE_TRANS = 21,
|
|
SP_EXPORT_VPC_TRANS = 22,
|
|
SP_EXPORT_RB_TRANS = 23,
|
|
SP_PIXELS_KILLED = 24,
|
|
SP_ICL1_REQUESTS = 25,
|
|
SP_ICL1_MISSES = 26,
|
|
SP_ICL0_REQUESTS = 27,
|
|
SP_ICL0_MISSES = 28,
|
|
SP_ALU_WORKING_CYCLES = 29,
|
|
SP_EFU_WORKING_CYCLES = 30,
|
|
SP_STALL_CYCLES_BY_VPC = 31,
|
|
SP_STALL_CYCLES_BY_TP = 32,
|
|
SP_STALL_CYCLES_BY_UCHE = 33,
|
|
SP_STALL_CYCLES_BY_RB = 34,
|
|
SP_BUSY_CYCLES = 35,
|
|
SP_HS_INSTRUCTIONS = 36,
|
|
SP_DS_INSTRUCTIONS = 37,
|
|
SP_GS_INSTRUCTIONS = 38,
|
|
SP_CS_INSTRUCTIONS = 39,
|
|
SP_SCHEDULER_NON_WORKING = 40,
|
|
SP_WAVE_CONTEXTS = 41,
|
|
SP_WAVE_CONTEXT_CYCLES = 42,
|
|
SP_POWER0 = 43,
|
|
SP_POWER1 = 44,
|
|
SP_POWER2 = 45,
|
|
SP_POWER3 = 46,
|
|
SP_POWER4 = 47,
|
|
SP_POWER5 = 48,
|
|
SP_POWER6 = 49,
|
|
SP_POWER7 = 50,
|
|
SP_POWER8 = 51,
|
|
SP_POWER9 = 52,
|
|
SP_POWER10 = 53,
|
|
SP_POWER11 = 54,
|
|
SP_POWER12 = 55,
|
|
SP_POWER13 = 56,
|
|
SP_POWER14 = 57,
|
|
SP_POWER15 = 58,
|
|
};
|
|
|
|
enum a4xx_tp_perfcounter_select {
|
|
TP_L1_REQUESTS = 0,
|
|
TP_L1_MISSES = 1,
|
|
TP_QUADS_OFFSET = 8,
|
|
TP_QUAD_SHADOW = 9,
|
|
TP_QUADS_ARRAY = 10,
|
|
TP_QUADS_GRADIENT = 11,
|
|
TP_QUADS_1D2D = 12,
|
|
TP_QUADS_3DCUBE = 13,
|
|
TP_BUSY_CYCLES = 16,
|
|
TP_STALL_CYCLES_BY_ARB = 17,
|
|
TP_STATE_CACHE_REQUESTS = 20,
|
|
TP_STATE_CACHE_MISSES = 21,
|
|
TP_POWER0 = 22,
|
|
TP_POWER1 = 23,
|
|
TP_POWER2 = 24,
|
|
TP_POWER3 = 25,
|
|
TP_POWER4 = 26,
|
|
TP_POWER5 = 27,
|
|
TP_POWER6 = 28,
|
|
TP_POWER7 = 29,
|
|
};
|
|
|
|
enum a4xx_uche_perfcounter_select {
|
|
UCHE_VBIF_READ_BEATS_TP = 0,
|
|
UCHE_VBIF_READ_BEATS_VFD = 1,
|
|
UCHE_VBIF_READ_BEATS_HLSQ = 2,
|
|
UCHE_VBIF_READ_BEATS_MARB = 3,
|
|
UCHE_VBIF_READ_BEATS_SP = 4,
|
|
UCHE_READ_REQUESTS_TP = 5,
|
|
UCHE_READ_REQUESTS_VFD = 6,
|
|
UCHE_READ_REQUESTS_HLSQ = 7,
|
|
UCHE_READ_REQUESTS_MARB = 8,
|
|
UCHE_READ_REQUESTS_SP = 9,
|
|
UCHE_WRITE_REQUESTS_MARB = 10,
|
|
UCHE_WRITE_REQUESTS_SP = 11,
|
|
UCHE_TAG_CHECK_FAILS = 12,
|
|
UCHE_EVICTS = 13,
|
|
UCHE_FLUSHES = 14,
|
|
UCHE_VBIF_LATENCY_CYCLES = 15,
|
|
UCHE_VBIF_LATENCY_SAMPLES = 16,
|
|
UCHE_BUSY_CYCLES = 17,
|
|
UCHE_VBIF_READ_BEATS_PC = 18,
|
|
UCHE_READ_REQUESTS_PC = 19,
|
|
UCHE_WRITE_REQUESTS_VPC = 20,
|
|
UCHE_STALL_BY_VBIF = 21,
|
|
UCHE_WRITE_REQUESTS_VSC = 22,
|
|
UCHE_POWER0 = 23,
|
|
UCHE_POWER1 = 24,
|
|
UCHE_POWER2 = 25,
|
|
UCHE_POWER3 = 26,
|
|
UCHE_POWER4 = 27,
|
|
UCHE_POWER5 = 28,
|
|
UCHE_POWER6 = 29,
|
|
UCHE_POWER7 = 30,
|
|
};
|
|
|
|
enum a4xx_vbif_perfcounter_select {
|
|
AXI_READ_REQUESTS_ID_0 = 0,
|
|
AXI_READ_REQUESTS_ID_1 = 1,
|
|
AXI_READ_REQUESTS_ID_2 = 2,
|
|
AXI_READ_REQUESTS_ID_3 = 3,
|
|
AXI_READ_REQUESTS_ID_4 = 4,
|
|
AXI_READ_REQUESTS_ID_5 = 5,
|
|
AXI_READ_REQUESTS_ID_6 = 6,
|
|
AXI_READ_REQUESTS_ID_7 = 7,
|
|
AXI_READ_REQUESTS_ID_8 = 8,
|
|
AXI_READ_REQUESTS_ID_9 = 9,
|
|
AXI_READ_REQUESTS_ID_10 = 10,
|
|
AXI_READ_REQUESTS_ID_11 = 11,
|
|
AXI_READ_REQUESTS_ID_12 = 12,
|
|
AXI_READ_REQUESTS_ID_13 = 13,
|
|
AXI_READ_REQUESTS_ID_14 = 14,
|
|
AXI_READ_REQUESTS_ID_15 = 15,
|
|
AXI0_READ_REQUESTS_TOTAL = 16,
|
|
AXI1_READ_REQUESTS_TOTAL = 17,
|
|
AXI2_READ_REQUESTS_TOTAL = 18,
|
|
AXI3_READ_REQUESTS_TOTAL = 19,
|
|
AXI_READ_REQUESTS_TOTAL = 20,
|
|
AXI_WRITE_REQUESTS_ID_0 = 21,
|
|
AXI_WRITE_REQUESTS_ID_1 = 22,
|
|
AXI_WRITE_REQUESTS_ID_2 = 23,
|
|
AXI_WRITE_REQUESTS_ID_3 = 24,
|
|
AXI_WRITE_REQUESTS_ID_4 = 25,
|
|
AXI_WRITE_REQUESTS_ID_5 = 26,
|
|
AXI_WRITE_REQUESTS_ID_6 = 27,
|
|
AXI_WRITE_REQUESTS_ID_7 = 28,
|
|
AXI_WRITE_REQUESTS_ID_8 = 29,
|
|
AXI_WRITE_REQUESTS_ID_9 = 30,
|
|
AXI_WRITE_REQUESTS_ID_10 = 31,
|
|
AXI_WRITE_REQUESTS_ID_11 = 32,
|
|
AXI_WRITE_REQUESTS_ID_12 = 33,
|
|
AXI_WRITE_REQUESTS_ID_13 = 34,
|
|
AXI_WRITE_REQUESTS_ID_14 = 35,
|
|
AXI_WRITE_REQUESTS_ID_15 = 36,
|
|
AXI0_WRITE_REQUESTS_TOTAL = 37,
|
|
AXI1_WRITE_REQUESTS_TOTAL = 38,
|
|
AXI2_WRITE_REQUESTS_TOTAL = 39,
|
|
AXI3_WRITE_REQUESTS_TOTAL = 40,
|
|
AXI_WRITE_REQUESTS_TOTAL = 41,
|
|
AXI_TOTAL_REQUESTS = 42,
|
|
AXI_READ_DATA_BEATS_ID_0 = 43,
|
|
AXI_READ_DATA_BEATS_ID_1 = 44,
|
|
AXI_READ_DATA_BEATS_ID_2 = 45,
|
|
AXI_READ_DATA_BEATS_ID_3 = 46,
|
|
AXI_READ_DATA_BEATS_ID_4 = 47,
|
|
AXI_READ_DATA_BEATS_ID_5 = 48,
|
|
AXI_READ_DATA_BEATS_ID_6 = 49,
|
|
AXI_READ_DATA_BEATS_ID_7 = 50,
|
|
AXI_READ_DATA_BEATS_ID_8 = 51,
|
|
AXI_READ_DATA_BEATS_ID_9 = 52,
|
|
AXI_READ_DATA_BEATS_ID_10 = 53,
|
|
AXI_READ_DATA_BEATS_ID_11 = 54,
|
|
AXI_READ_DATA_BEATS_ID_12 = 55,
|
|
AXI_READ_DATA_BEATS_ID_13 = 56,
|
|
AXI_READ_DATA_BEATS_ID_14 = 57,
|
|
AXI_READ_DATA_BEATS_ID_15 = 58,
|
|
AXI0_READ_DATA_BEATS_TOTAL = 59,
|
|
AXI1_READ_DATA_BEATS_TOTAL = 60,
|
|
AXI2_READ_DATA_BEATS_TOTAL = 61,
|
|
AXI3_READ_DATA_BEATS_TOTAL = 62,
|
|
AXI_READ_DATA_BEATS_TOTAL = 63,
|
|
AXI_WRITE_DATA_BEATS_ID_0 = 64,
|
|
AXI_WRITE_DATA_BEATS_ID_1 = 65,
|
|
AXI_WRITE_DATA_BEATS_ID_2 = 66,
|
|
AXI_WRITE_DATA_BEATS_ID_3 = 67,
|
|
AXI_WRITE_DATA_BEATS_ID_4 = 68,
|
|
AXI_WRITE_DATA_BEATS_ID_5 = 69,
|
|
AXI_WRITE_DATA_BEATS_ID_6 = 70,
|
|
AXI_WRITE_DATA_BEATS_ID_7 = 71,
|
|
AXI_WRITE_DATA_BEATS_ID_8 = 72,
|
|
AXI_WRITE_DATA_BEATS_ID_9 = 73,
|
|
AXI_WRITE_DATA_BEATS_ID_10 = 74,
|
|
AXI_WRITE_DATA_BEATS_ID_11 = 75,
|
|
AXI_WRITE_DATA_BEATS_ID_12 = 76,
|
|
AXI_WRITE_DATA_BEATS_ID_13 = 77,
|
|
AXI_WRITE_DATA_BEATS_ID_14 = 78,
|
|
AXI_WRITE_DATA_BEATS_ID_15 = 79,
|
|
AXI0_WRITE_DATA_BEATS_TOTAL = 80,
|
|
AXI1_WRITE_DATA_BEATS_TOTAL = 81,
|
|
AXI2_WRITE_DATA_BEATS_TOTAL = 82,
|
|
AXI3_WRITE_DATA_BEATS_TOTAL = 83,
|
|
AXI_WRITE_DATA_BEATS_TOTAL = 84,
|
|
AXI_DATA_BEATS_TOTAL = 85,
|
|
CYCLES_HELD_OFF_ID_0 = 86,
|
|
CYCLES_HELD_OFF_ID_1 = 87,
|
|
CYCLES_HELD_OFF_ID_2 = 88,
|
|
CYCLES_HELD_OFF_ID_3 = 89,
|
|
CYCLES_HELD_OFF_ID_4 = 90,
|
|
CYCLES_HELD_OFF_ID_5 = 91,
|
|
CYCLES_HELD_OFF_ID_6 = 92,
|
|
CYCLES_HELD_OFF_ID_7 = 93,
|
|
CYCLES_HELD_OFF_ID_8 = 94,
|
|
CYCLES_HELD_OFF_ID_9 = 95,
|
|
CYCLES_HELD_OFF_ID_10 = 96,
|
|
CYCLES_HELD_OFF_ID_11 = 97,
|
|
CYCLES_HELD_OFF_ID_12 = 98,
|
|
CYCLES_HELD_OFF_ID_13 = 99,
|
|
CYCLES_HELD_OFF_ID_14 = 100,
|
|
CYCLES_HELD_OFF_ID_15 = 101,
|
|
AXI_READ_REQUEST_HELD_OFF = 102,
|
|
AXI_WRITE_REQUEST_HELD_OFF = 103,
|
|
AXI_REQUEST_HELD_OFF = 104,
|
|
AXI_WRITE_DATA_HELD_OFF = 105,
|
|
OCMEM_AXI_READ_REQUEST_HELD_OFF = 106,
|
|
OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107,
|
|
OCMEM_AXI_REQUEST_HELD_OFF = 108,
|
|
OCMEM_AXI_WRITE_DATA_HELD_OFF = 109,
|
|
ELAPSED_CYCLES_DDR = 110,
|
|
ELAPSED_CYCLES_OCMEM = 111,
|
|
};
|
|
|
|
enum a4xx_vfd_perfcounter_select {
|
|
VFD_UCHE_BYTE_FETCHED = 0,
|
|
VFD_UCHE_TRANS = 1,
|
|
VFD_FETCH_INSTRUCTIONS = 3,
|
|
VFD_BUSY_CYCLES = 5,
|
|
VFD_STALL_CYCLES_UCHE = 6,
|
|
VFD_STALL_CYCLES_HLSQ = 7,
|
|
VFD_STALL_CYCLES_VPC_BYPASS = 8,
|
|
VFD_STALL_CYCLES_VPC_ALLOC = 9,
|
|
VFD_MODE_0_FIBERS = 13,
|
|
VFD_MODE_1_FIBERS = 14,
|
|
VFD_MODE_2_FIBERS = 15,
|
|
VFD_MODE_3_FIBERS = 16,
|
|
VFD_MODE_4_FIBERS = 17,
|
|
VFD_BFIFO_STALL = 18,
|
|
VFD_NUM_VERTICES_TOTAL = 19,
|
|
VFD_PACKER_FULL = 20,
|
|
VFD_UCHE_REQUEST_FIFO_FULL = 21,
|
|
VFD_STARVE_CYCLES_PC = 22,
|
|
VFD_STARVE_CYCLES_UCHE = 23,
|
|
};
|
|
|
|
enum a4xx_vpc_perfcounter_select {
|
|
VPC_SP_LM_COMPONENTS = 2,
|
|
VPC_SP0_LM_BYTES = 3,
|
|
VPC_SP1_LM_BYTES = 4,
|
|
VPC_SP2_LM_BYTES = 5,
|
|
VPC_SP3_LM_BYTES = 6,
|
|
VPC_WORKING_CYCLES = 7,
|
|
VPC_STALL_CYCLES_LM = 8,
|
|
VPC_STARVE_CYCLES_RAS = 9,
|
|
VPC_STREAMOUT_CYCLES = 10,
|
|
VPC_UCHE_TRANSACTIONS = 12,
|
|
VPC_STALL_CYCLES_UCHE = 13,
|
|
VPC_BUSY_CYCLES = 14,
|
|
VPC_STARVE_CYCLES_SP = 15,
|
|
};
|
|
|
|
enum a4xx_vsc_perfcounter_select {
|
|
VSC_BUSY_CYCLES = 0,
|
|
VSC_WORKING_CYCLES = 1,
|
|
VSC_STALL_CYCLES_UCHE = 2,
|
|
VSC_STARVE_CYCLES_RAS = 3,
|
|
VSC_EOT_NUM = 4,
|
|
};
|
|
|
|
enum a4xx_tex_filter {
|
|
A4XX_TEX_NEAREST = 0,
|
|
A4XX_TEX_LINEAR = 1,
|
|
A4XX_TEX_ANISO = 2,
|
|
};
|
|
|
|
enum a4xx_tex_clamp {
|
|
A4XX_TEX_REPEAT = 0,
|
|
A4XX_TEX_CLAMP_TO_EDGE = 1,
|
|
A4XX_TEX_MIRROR_REPEAT = 2,
|
|
A4XX_TEX_CLAMP_TO_BORDER = 3,
|
|
A4XX_TEX_MIRROR_CLAMP = 4,
|
|
};
|
|
|
|
enum a4xx_tex_aniso {
|
|
A4XX_TEX_ANISO_1 = 0,
|
|
A4XX_TEX_ANISO_2 = 1,
|
|
A4XX_TEX_ANISO_4 = 2,
|
|
A4XX_TEX_ANISO_8 = 3,
|
|
A4XX_TEX_ANISO_16 = 4,
|
|
};
|
|
|
|
enum a4xx_tex_swiz {
|
|
A4XX_TEX_X = 0,
|
|
A4XX_TEX_Y = 1,
|
|
A4XX_TEX_Z = 2,
|
|
A4XX_TEX_W = 3,
|
|
A4XX_TEX_ZERO = 4,
|
|
A4XX_TEX_ONE = 5,
|
|
};
|
|
|
|
enum a4xx_tex_type {
|
|
A4XX_TEX_1D = 0,
|
|
A4XX_TEX_2D = 1,
|
|
A4XX_TEX_CUBE = 2,
|
|
A4XX_TEX_3D = 3,
|
|
};
|
|
|
|
#define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000
|
|
#define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20
|
|
static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
|
|
}
|
|
#define A4XX_INT0_RBBM_GPU_IDLE 0x00000001
|
|
#define A4XX_INT0_RBBM_AHB_ERROR 0x00000002
|
|
#define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004
|
|
#define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
|
|
#define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
|
|
#define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
|
|
#define A4XX_INT0_VFD_ERROR 0x00000040
|
|
#define A4XX_INT0_CP_SW_INT 0x00000080
|
|
#define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
|
|
#define A4XX_INT0_CP_OPCODE_ERROR 0x00000200
|
|
#define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
|
|
#define A4XX_INT0_CP_HW_FAULT 0x00000800
|
|
#define A4XX_INT0_CP_DMA 0x00001000
|
|
#define A4XX_INT0_CP_IB2_INT 0x00002000
|
|
#define A4XX_INT0_CP_IB1_INT 0x00004000
|
|
#define A4XX_INT0_CP_RB_INT 0x00008000
|
|
#define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
|
|
#define A4XX_INT0_CP_RB_DONE_TS 0x00020000
|
|
#define A4XX_INT0_CP_VS_DONE_TS 0x00040000
|
|
#define A4XX_INT0_CP_PS_DONE_TS 0x00080000
|
|
#define A4XX_INT0_CACHE_FLUSH_TS 0x00100000
|
|
#define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000
|
|
#define A4XX_INT0_MISC_HANG_DETECT 0x01000000
|
|
#define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000
|
|
#define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0
|
|
|
|
#define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7
|
|
|
|
#define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8
|
|
|
|
#define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9
|
|
|
|
#define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca
|
|
|
|
#define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb
|
|
|
|
#define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc
|
|
|
|
#define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd
|
|
|
|
#define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
|
|
|
|
#define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf
|
|
|
|
#define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0
|
|
|
|
#define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1
|
|
|
|
#define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
|
|
|
|
#define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
|
|
#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
|
|
#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
|
|
static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
|
|
}
|
|
#define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000
|
|
#define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16
|
|
static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc
|
|
|
|
#define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd
|
|
|
|
#define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce
|
|
|
|
#define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf
|
|
|
|
#define REG_A4XX_RB_MODE_CONTROL 0x000020a0
|
|
#define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f
|
|
#define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0
|
|
static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
|
|
}
|
|
#define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00
|
|
#define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8
|
|
static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_RENDER_CONTROL 0x000020a1
|
|
#define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001
|
|
#define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020
|
|
|
|
#define REG_A4XX_RB_MSAA_CONTROL 0x000020a2
|
|
#define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000
|
|
#define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000
|
|
#define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13
|
|
static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
|
|
#define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001
|
|
#define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002
|
|
#define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004
|
|
#define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008
|
|
#define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010
|
|
#define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
|
|
#define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040
|
|
#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380
|
|
#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7
|
|
static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
|
|
}
|
|
#define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800
|
|
#define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000
|
|
|
|
static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
|
|
#define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
|
|
#define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
|
|
#define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
|
|
#define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040
|
|
#define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
|
|
#define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
|
|
static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
|
|
{
|
|
return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK;
|
|
}
|
|
#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
|
|
#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
|
|
static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
|
|
#define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
|
|
#define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
|
|
static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
|
|
{
|
|
return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
|
|
}
|
|
#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
|
|
#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
|
|
static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
|
|
{
|
|
return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
|
|
}
|
|
#define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600
|
|
#define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9
|
|
static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
|
|
{
|
|
return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
|
|
}
|
|
#define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800
|
|
#define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11
|
|
static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
|
|
}
|
|
#define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000
|
|
#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000
|
|
#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14
|
|
static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
|
|
#define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8
|
|
#define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3
|
|
static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
|
|
#define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
|
|
#define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
|
|
static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
|
|
{
|
|
return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
|
|
}
|
|
#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
|
|
#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
|
|
static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
|
|
{
|
|
return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
|
|
}
|
|
#define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
|
|
#define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
|
|
static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
|
|
{
|
|
return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
|
|
}
|
|
#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
|
|
#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
|
|
static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
|
|
{
|
|
return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
|
|
}
|
|
#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
|
|
#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
|
|
static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
|
|
{
|
|
return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
|
|
}
|
|
#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
|
|
#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
|
|
static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
|
|
{
|
|
return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_BLEND_RED 0x000020f0
|
|
#define A4XX_RB_BLEND_RED_UINT__MASK 0x0000ffff
|
|
#define A4XX_RB_BLEND_RED_UINT__SHIFT 0
|
|
static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
|
|
}
|
|
#define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
|
|
#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
|
|
static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
|
|
{
|
|
return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
|
|
#define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff
|
|
#define A4XX_RB_BLEND_RED_F32__SHIFT 0
|
|
static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
|
|
{
|
|
return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_BLEND_GREEN 0x000020f2
|
|
#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x0000ffff
|
|
#define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
|
|
static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
|
|
}
|
|
#define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
|
|
#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
|
|
static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
|
|
{
|
|
return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
|
|
#define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
|
|
#define A4XX_RB_BLEND_GREEN_F32__SHIFT 0
|
|
static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
|
|
{
|
|
return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_BLEND_BLUE 0x000020f4
|
|
#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x0000ffff
|
|
#define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
|
|
static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
|
|
}
|
|
#define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
|
|
#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
|
|
static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
|
|
{
|
|
return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
|
|
#define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
|
|
#define A4XX_RB_BLEND_BLUE_F32__SHIFT 0
|
|
static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
|
|
{
|
|
return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
|
|
#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x0000ffff
|
|
#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
|
|
static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
|
|
}
|
|
#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
|
|
#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
|
|
static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
|
|
{
|
|
return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
|
|
#define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
|
|
#define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0
|
|
static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
|
|
{
|
|
return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
|
|
#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
|
|
#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
|
|
static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
|
|
}
|
|
#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
|
|
#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
|
|
#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
|
|
static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
|
|
{
|
|
return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_FS_OUTPUT 0x000020f9
|
|
#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff
|
|
#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0
|
|
static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
|
|
}
|
|
#define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100
|
|
#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
|
|
#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16
|
|
static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa
|
|
#define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
|
|
#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc
|
|
#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2
|
|
static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
|
|
{
|
|
return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
|
|
static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
|
|
}
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
|
|
static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
|
|
}
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
|
|
static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
|
|
}
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
|
|
static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
|
|
}
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
|
|
static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
|
|
}
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
|
|
static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
|
|
}
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
|
|
static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
|
|
}
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
|
|
#define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
|
|
static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_COPY_CONTROL 0x000020fc
|
|
#define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
|
|
#define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
|
|
static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
|
|
}
|
|
#define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
|
|
#define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4
|
|
static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
|
|
{
|
|
return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK;
|
|
}
|
|
#define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
|
|
#define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
|
|
static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
|
|
}
|
|
#define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
|
|
#define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
|
|
static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
|
|
{
|
|
return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd
|
|
#define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0
|
|
#define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5
|
|
static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe
|
|
#define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
|
|
#define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
|
|
static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff
|
|
#define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
|
|
#define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
|
|
static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
|
|
{
|
|
return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK;
|
|
}
|
|
#define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
|
|
#define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
|
|
static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK;
|
|
}
|
|
#define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
|
|
#define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
|
|
static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
|
|
{
|
|
return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
|
|
}
|
|
#define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
|
|
#define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
|
|
static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
|
|
}
|
|
#define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
|
|
#define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
|
|
static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
|
|
{
|
|
return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
|
|
}
|
|
#define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000
|
|
#define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24
|
|
static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
|
|
{
|
|
return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100
|
|
#define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f
|
|
#define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0
|
|
static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
|
|
}
|
|
#define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020
|
|
|
|
#define REG_A4XX_RB_DEPTH_CONTROL 0x00002101
|
|
#define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
|
|
#define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
|
|
#define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
|
|
#define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
|
|
#define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
|
|
static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
|
|
{
|
|
return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
|
|
}
|
|
#define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
|
|
#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
|
|
#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000
|
|
#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
|
|
|
|
#define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
|
|
|
|
#define REG_A4XX_RB_DEPTH_INFO 0x00002103
|
|
#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
|
|
#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
|
|
static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
|
|
{
|
|
return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
|
|
}
|
|
#define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
|
|
#define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
|
|
static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
|
|
{
|
|
return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_DEPTH_PITCH 0x00002104
|
|
#define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff
|
|
#define A4XX_RB_DEPTH_PITCH__SHIFT 0
|
|
static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_DEPTH_PITCH2 0x00002105
|
|
#define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff
|
|
#define A4XX_RB_DEPTH_PITCH2__SHIFT 0
|
|
static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_STENCIL_CONTROL 0x00002106
|
|
#define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
|
|
#define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
|
|
#define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
|
|
#define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
|
|
#define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
|
|
static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
|
|
{
|
|
return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK;
|
|
}
|
|
#define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
|
|
#define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
|
|
static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK;
|
|
}
|
|
#define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
|
|
#define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
|
|
static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK;
|
|
}
|
|
#define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
|
|
#define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
|
|
static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
|
|
}
|
|
#define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
|
|
#define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
|
|
static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
|
|
{
|
|
return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
|
|
}
|
|
#define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
|
|
#define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
|
|
static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
|
|
}
|
|
#define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
|
|
#define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
|
|
static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
|
|
}
|
|
#define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
|
|
#define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
|
|
static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107
|
|
#define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001
|
|
|
|
#define REG_A4XX_RB_STENCIL_INFO 0x00002108
|
|
#define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
|
|
#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000
|
|
#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12
|
|
static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
|
|
{
|
|
return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_STENCIL_PITCH 0x00002109
|
|
#define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff
|
|
#define A4XX_RB_STENCIL_PITCH__SHIFT 0
|
|
static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_STENCILREFMASK 0x0000210b
|
|
#define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
|
|
#define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
|
|
static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK;
|
|
}
|
|
#define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
|
|
#define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
|
|
static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK;
|
|
}
|
|
#define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
|
|
#define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
|
|
static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c
|
|
#define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
|
|
#define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
|
|
static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
|
|
}
|
|
#define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
|
|
#define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
|
|
static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
|
|
}
|
|
#define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
|
|
#define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
|
|
static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_RB_BIN_OFFSET 0x0000210d
|
|
#define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff
|
|
#define A4XX_RB_BIN_OFFSET_X__SHIFT 0
|
|
static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK;
|
|
}
|
|
#define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000
|
|
#define A4XX_RB_BIN_OFFSET_Y__SHIFT 16
|
|
static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
|
|
|
|
#define REG_A4XX_RBBM_HW_VERSION 0x00000000
|
|
|
|
#define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_CTL 0x00000020
|
|
|
|
#define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021
|
|
|
|
#define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022
|
|
|
|
#define REG_A4XX_RBBM_AHB_CTL0 0x00000023
|
|
|
|
#define REG_A4XX_RBBM_AHB_CTL1 0x00000024
|
|
|
|
#define REG_A4XX_RBBM_AHB_CMD 0x00000025
|
|
|
|
#define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026
|
|
|
|
#define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028
|
|
|
|
#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b
|
|
|
|
#define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f
|
|
|
|
#define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034
|
|
|
|
#define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036
|
|
|
|
#define REG_A4XX_RBBM_INT_0_MASK 0x00000037
|
|
|
|
#define REG_A4XX_RBBM_RBBM_CTL 0x0000003e
|
|
|
|
#define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f
|
|
|
|
#define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042
|
|
|
|
#define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
|
|
|
|
#define REG_A4XX_RBBM_RESET_CYCLES 0x00000047
|
|
|
|
#define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049
|
|
|
|
#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a
|
|
|
|
#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b
|
|
|
|
#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c
|
|
|
|
#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
|
|
|
|
#define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098
|
|
#define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001
|
|
#define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169
|
|
|
|
#define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e
|
|
|
|
#define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
|
|
|
|
#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099
|
|
|
|
#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178
|
|
|
|
#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179
|
|
|
|
#define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
|
|
|
|
#define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
|
|
|
|
#define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182
|
|
|
|
#define REG_A4XX_RBBM_AHB_STATUS 0x00000189
|
|
|
|
#define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c
|
|
|
|
#define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d
|
|
|
|
#define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f
|
|
|
|
#define REG_A4XX_RBBM_STATUS 0x00000191
|
|
#define A4XX_RBBM_STATUS_HI_BUSY 0x00000001
|
|
#define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
|
|
#define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
|
|
#define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
|
|
#define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000
|
|
#define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000
|
|
#define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000
|
|
#define A4XX_RBBM_STATUS_RB_BUSY 0x00040000
|
|
#define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
|
|
#define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
|
|
#define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000
|
|
#define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000
|
|
#define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000
|
|
#define A4XX_RBBM_STATUS_SP_BUSY 0x01000000
|
|
#define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000
|
|
#define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000
|
|
#define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000
|
|
#define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000
|
|
#define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
|
|
#define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
|
|
#define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000
|
|
|
|
#define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
|
|
|
|
#define REG_A4XX_RBBM_POWER_STATUS 0x000001b0
|
|
#define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000
|
|
|
|
#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8
|
|
|
|
#define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
|
|
|
|
#define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
|
|
|
|
#define REG_A4XX_CP_RB_BASE 0x00000200
|
|
|
|
#define REG_A4XX_CP_RB_CNTL 0x00000201
|
|
|
|
#define REG_A4XX_CP_RB_WPTR 0x00000205
|
|
|
|
#define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203
|
|
|
|
#define REG_A4XX_CP_RB_RPTR 0x00000204
|
|
|
|
#define REG_A4XX_CP_IB1_BASE 0x00000206
|
|
|
|
#define REG_A4XX_CP_IB1_BUFSZ 0x00000207
|
|
|
|
#define REG_A4XX_CP_IB2_BASE 0x00000208
|
|
|
|
#define REG_A4XX_CP_IB2_BUFSZ 0x00000209
|
|
|
|
#define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c
|
|
|
|
#define REG_A4XX_CP_ME_NRT_DATA 0x0000020d
|
|
|
|
#define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217
|
|
|
|
#define REG_A4XX_CP_QUEUE_THRESH2 0x00000219
|
|
|
|
#define REG_A4XX_CP_MERCIU_SIZE 0x0000021b
|
|
|
|
#define REG_A4XX_CP_ROQ_ADDR 0x0000021c
|
|
|
|
#define REG_A4XX_CP_ROQ_DATA 0x0000021d
|
|
|
|
#define REG_A4XX_CP_MEQ_ADDR 0x0000021e
|
|
|
|
#define REG_A4XX_CP_MEQ_DATA 0x0000021f
|
|
|
|
#define REG_A4XX_CP_MERCIU_ADDR 0x00000220
|
|
|
|
#define REG_A4XX_CP_MERCIU_DATA 0x00000221
|
|
|
|
#define REG_A4XX_CP_MERCIU_DATA2 0x00000222
|
|
|
|
#define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223
|
|
|
|
#define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224
|
|
|
|
#define REG_A4XX_CP_ME_RAM_WADDR 0x00000225
|
|
|
|
#define REG_A4XX_CP_ME_RAM_RADDR 0x00000226
|
|
|
|
#define REG_A4XX_CP_ME_RAM_DATA 0x00000227
|
|
|
|
#define REG_A4XX_CP_PREEMPT 0x0000022a
|
|
|
|
#define REG_A4XX_CP_CNTL 0x0000022c
|
|
|
|
#define REG_A4XX_CP_ME_CNTL 0x0000022d
|
|
|
|
#define REG_A4XX_CP_DEBUG 0x0000022e
|
|
|
|
#define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231
|
|
|
|
#define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232
|
|
|
|
#define REG_A4XX_CP_PROTECT_REG_0 0x00000240
|
|
|
|
static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
|
|
|
|
#define REG_A4XX_CP_PROTECT_CTRL 0x00000250
|
|
|
|
#define REG_A4XX_CP_ST_BASE 0x000004c0
|
|
|
|
#define REG_A4XX_CP_STQ_AVAIL 0x000004ce
|
|
|
|
#define REG_A4XX_CP_MERCIU_STAT 0x000004d0
|
|
|
|
#define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2
|
|
|
|
#define REG_A4XX_CP_HW_FAULT 0x000004d8
|
|
|
|
#define REG_A4XX_CP_PROTECT_STATUS 0x000004da
|
|
|
|
#define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd
|
|
|
|
#define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
|
|
|
|
#define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501
|
|
|
|
#define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502
|
|
|
|
#define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503
|
|
|
|
#define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504
|
|
|
|
#define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505
|
|
|
|
#define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506
|
|
|
|
#define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507
|
|
|
|
#define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
|
|
|
|
static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
|
|
|
|
#define REG_A4XX_SP_VS_STATUS 0x00000ec0
|
|
|
|
#define REG_A4XX_SP_MODE_CONTROL 0x00000ec3
|
|
|
|
#define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4
|
|
|
|
#define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5
|
|
|
|
#define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6
|
|
|
|
#define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7
|
|
|
|
#define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8
|
|
|
|
#define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9
|
|
|
|
#define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca
|
|
|
|
#define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb
|
|
|
|
#define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc
|
|
|
|
#define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd
|
|
|
|
#define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece
|
|
|
|
#define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
|
|
|
|
#define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
|
|
#define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000
|
|
|
|
#define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1
|
|
#define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080
|
|
#define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100
|
|
#define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400
|
|
|
|
#define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4
|
|
#define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
|
|
#define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
|
|
static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
|
|
}
|
|
#define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002
|
|
#define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
|
|
#define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
|
|
#define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
|
|
static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
|
}
|
|
#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
|
|
#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
|
|
static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
|
}
|
|
#define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
|
|
#define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
|
|
static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
|
|
}
|
|
#define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
|
|
#define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
|
|
static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
|
|
}
|
|
#define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
|
|
#define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
|
|
|
|
#define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5
|
|
#define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
|
|
#define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
|
|
static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
|
|
}
|
|
#define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
|
|
#define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
|
|
static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_SP_VS_PARAM_REG 0x000022c6
|
|
#define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
|
|
#define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
|
|
static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK;
|
|
}
|
|
#define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
|
|
#define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
|
|
static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
|
|
}
|
|
#define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
|
|
#define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
|
|
static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
|
|
#define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
|
|
#define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
|
|
static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK;
|
|
}
|
|
#define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
|
|
#define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
|
|
static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
|
|
}
|
|
#define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
|
|
#define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
|
|
static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK;
|
|
}
|
|
#define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
|
|
#define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
|
|
static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
|
|
#define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
|
|
#define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
|
|
static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
|
|
}
|
|
#define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
|
|
#define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
|
|
static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
|
|
}
|
|
#define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
|
|
#define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
|
|
static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
|
|
}
|
|
#define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
|
|
#define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
|
|
static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0
|
|
#define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
|
|
#define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
|
|
static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
|
|
#define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
|
|
static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_SP_VS_OBJ_START 0x000022e1
|
|
|
|
#define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2
|
|
|
|
#define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3
|
|
|
|
#define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5
|
|
|
|
#define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8
|
|
#define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
|
|
#define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
|
|
static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
|
|
{
|
|
return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
|
|
}
|
|
#define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002
|
|
#define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
|
|
#define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
|
|
#define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
|
|
static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
|
}
|
|
#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
|
|
#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
|
|
static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
|
}
|
|
#define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
|
|
#define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
|
|
static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
|
|
}
|
|
#define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
|
|
#define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
|
|
static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
|
{
|
|
return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
|
|
}
|
|
#define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
|
|
#define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
|
|
|
|
#define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9
|
|
#define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
|
|
#define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
|
|
static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
|
|
}
|
|
#define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000
|
|
#define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000
|
|
#define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000
|
|
|
|
#define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea
|
|
#define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
|
|
#define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
|
|
static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
|
|
#define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
|
|
static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_SP_FS_OBJ_START 0x000022eb
|
|
|
|
#define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec
|
|
|
|
#define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed
|
|
|
|
#define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef
|
|
|
|
#define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0
|
|
#define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f
|
|
#define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
|
|
static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
|
|
}
|
|
#define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
|
|
#define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
|
|
#define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
|
|
static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
|
|
}
|
|
#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000
|
|
#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24
|
|
static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
|
|
#define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
|
|
#define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0
|
|
static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
|
|
}
|
|
#define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
|
|
#define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000
|
|
#define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12
|
|
static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
|
|
{
|
|
return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
|
|
}
|
|
#define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
|
|
|
|
#define REG_A4XX_SP_CS_CTRL_REG0 0x00002300
|
|
|
|
#define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301
|
|
|
|
#define REG_A4XX_SP_CS_OBJ_START 0x00002302
|
|
|
|
#define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303
|
|
|
|
#define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304
|
|
|
|
#define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305
|
|
|
|
#define REG_A4XX_SP_CS_LENGTH_REG 0x00002306
|
|
|
|
#define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d
|
|
#define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
|
|
#define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
|
|
static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
|
|
#define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
|
|
static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_SP_HS_OBJ_START 0x0000230e
|
|
|
|
#define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f
|
|
|
|
#define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310
|
|
|
|
#define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
|
|
|
|
#define REG_A4XX_SP_DS_PARAM_REG 0x0000231a
|
|
#define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff
|
|
#define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0
|
|
static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;
|
|
}
|
|
#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
|
|
#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
|
|
static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
|
|
#define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff
|
|
#define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
|
|
static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;
|
|
}
|
|
#define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00
|
|
#define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9
|
|
static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
|
|
}
|
|
#define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000
|
|
#define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
|
|
static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;
|
|
}
|
|
#define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000
|
|
#define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25
|
|
static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
|
|
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
|
|
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
|
|
static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
|
|
}
|
|
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
|
|
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
|
|
static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
|
|
}
|
|
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
|
|
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
|
|
static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
|
|
}
|
|
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
|
|
#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
|
|
static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
|
|
#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
|
|
#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
|
|
static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
|
|
#define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
|
|
static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_SP_DS_OBJ_START 0x00002335
|
|
|
|
#define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336
|
|
|
|
#define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337
|
|
|
|
#define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
|
|
|
|
#define REG_A4XX_SP_GS_PARAM_REG 0x00002341
|
|
#define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff
|
|
#define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0
|
|
static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;
|
|
}
|
|
#define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00
|
|
#define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8
|
|
static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;
|
|
}
|
|
#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
|
|
#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
|
|
static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
|
|
#define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff
|
|
#define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
|
|
static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;
|
|
}
|
|
#define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00
|
|
#define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9
|
|
static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
|
|
}
|
|
#define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000
|
|
#define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
|
|
static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;
|
|
}
|
|
#define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000
|
|
#define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25
|
|
static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
|
|
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
|
|
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
|
|
static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
|
|
}
|
|
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
|
|
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
|
|
static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
|
|
}
|
|
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
|
|
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
|
|
static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
|
|
}
|
|
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
|
|
#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
|
|
static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
|
|
#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
|
|
#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
|
|
static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
|
|
#define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
|
|
static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_SP_GS_OBJ_START 0x0000235c
|
|
|
|
#define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d
|
|
|
|
#define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e
|
|
|
|
#define REG_A4XX_SP_GS_LENGTH_REG 0x00002360
|
|
|
|
#define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60
|
|
|
|
#define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61
|
|
|
|
#define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
|
|
|
|
#define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65
|
|
|
|
#define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66
|
|
|
|
#define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67
|
|
|
|
#define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
|
|
|
|
#define REG_A4XX_VPC_ATTR 0x00002140
|
|
#define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
|
|
#define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0
|
|
static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;
|
|
}
|
|
#define A4XX_VPC_ATTR_PSIZE 0x00000200
|
|
#define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000
|
|
#define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12
|
|
static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK;
|
|
}
|
|
#define A4XX_VPC_ATTR_ENABLE 0x02000000
|
|
|
|
#define REG_A4XX_VPC_PACK 0x00002141
|
|
#define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff
|
|
#define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0
|
|
static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK;
|
|
}
|
|
#define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
|
|
#define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
|
|
static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
|
|
}
|
|
#define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
|
|
#define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
|
|
static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
|
|
|
|
#define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e
|
|
|
|
#define REG_A4XX_VSC_BIN_SIZE 0x00000c00
|
|
#define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
|
|
#define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
|
|
static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
|
|
}
|
|
#define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
|
|
#define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
|
|
static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01
|
|
|
|
#define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02
|
|
|
|
#define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03
|
|
|
|
static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
|
|
#define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
|
|
#define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
|
|
static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK;
|
|
}
|
|
#define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
|
|
#define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
|
|
static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK;
|
|
}
|
|
#define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
|
|
#define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
|
|
static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK;
|
|
}
|
|
#define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
|
|
#define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
|
|
static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
|
|
|
|
#define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41
|
|
|
|
#define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50
|
|
|
|
#define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51
|
|
|
|
#define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
|
|
|
|
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43
|
|
|
|
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44
|
|
|
|
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45
|
|
|
|
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46
|
|
|
|
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47
|
|
|
|
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48
|
|
|
|
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49
|
|
|
|
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
|
|
|
|
#define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
|
|
|
|
#define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9
|
|
|
|
#define REG_A4XX_VFD_CONTROL_0 0x00002200
|
|
#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff
|
|
#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
|
|
static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
|
|
}
|
|
#define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00
|
|
#define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9
|
|
static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK;
|
|
}
|
|
#define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000
|
|
#define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20
|
|
static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
|
|
}
|
|
#define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000
|
|
#define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26
|
|
static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_VFD_CONTROL_1 0x00002201
|
|
#define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
|
|
#define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
|
|
static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
|
|
}
|
|
#define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
|
|
#define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
|
|
static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK;
|
|
}
|
|
#define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
|
|
#define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
|
|
static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_VFD_CONTROL_2 0x00002202
|
|
|
|
#define REG_A4XX_VFD_CONTROL_3 0x00002203
|
|
#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00
|
|
#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8
|
|
static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
|
|
}
|
|
#define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
|
|
#define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
|
|
static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;
|
|
}
|
|
#define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
|
|
#define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
|
|
static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_VFD_CONTROL_4 0x00002204
|
|
|
|
#define REG_A4XX_VFD_INDEX_OFFSET 0x00002208
|
|
|
|
static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
|
|
#define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
|
|
#define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
|
|
static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
|
|
}
|
|
#define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
|
|
#define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
|
|
static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
|
|
}
|
|
#define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000
|
|
#define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000
|
|
|
|
static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
|
|
#define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0
|
|
#define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4
|
|
static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
|
|
{
|
|
return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
|
|
#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff
|
|
#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0
|
|
static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
|
|
#define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
|
|
#define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
|
|
static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
|
|
}
|
|
#define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
|
|
#define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
|
|
#define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
|
|
static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
|
|
{
|
|
return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK;
|
|
}
|
|
#define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
|
|
#define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12
|
|
static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
|
|
}
|
|
#define A4XX_VFD_DECODE_INSTR_INT 0x00100000
|
|
#define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
|
|
#define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
|
|
static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK;
|
|
}
|
|
#define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
|
|
#define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
|
|
static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
|
|
}
|
|
#define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
|
|
#define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
|
|
|
|
#define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00
|
|
|
|
#define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03
|
|
|
|
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04
|
|
|
|
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05
|
|
|
|
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06
|
|
|
|
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07
|
|
|
|
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08
|
|
|
|
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09
|
|
|
|
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a
|
|
|
|
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
|
|
|
|
#define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
|
|
|
|
#define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
|
|
#define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
|
|
#define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
|
|
static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
|
|
}
|
|
#define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00
|
|
#define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8
|
|
static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
|
|
}
|
|
#define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000
|
|
#define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16
|
|
static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
|
|
}
|
|
#define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000
|
|
#define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24
|
|
static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384
|
|
|
|
#define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387
|
|
|
|
#define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a
|
|
|
|
#define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d
|
|
|
|
#define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0
|
|
|
|
#define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1
|
|
|
|
#define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4
|
|
|
|
#define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5
|
|
|
|
#define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
|
|
|
|
#define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
|
|
|
|
#define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81
|
|
|
|
#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
|
|
|
|
#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89
|
|
|
|
#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a
|
|
|
|
#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
|
|
|
|
#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c
|
|
|
|
#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d
|
|
|
|
#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e
|
|
|
|
#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f
|
|
|
|
#define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
|
|
#define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000
|
|
#define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
|
|
|
|
#define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003
|
|
#define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001
|
|
|
|
#define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
|
|
#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
|
|
#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
|
|
}
|
|
#define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
|
|
#define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
|
|
static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008
|
|
#define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
|
|
#define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
|
|
{
|
|
return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009
|
|
#define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
|
|
#define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
|
|
{
|
|
return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a
|
|
#define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
|
|
#define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
|
|
{
|
|
return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b
|
|
#define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
|
|
#define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
|
|
{
|
|
return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c
|
|
#define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
|
|
#define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
|
|
{
|
|
return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d
|
|
#define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
|
|
#define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
|
|
{
|
|
return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070
|
|
#define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
|
|
#define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
|
|
{
|
|
return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
|
|
}
|
|
#define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
|
|
#define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
|
|
static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
|
|
{
|
|
return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071
|
|
#define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
|
|
#define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
|
|
{
|
|
return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
|
|
#define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
|
|
#define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008
|
|
|
|
#define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
|
|
#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
|
|
#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
|
|
{
|
|
return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075
|
|
#define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
|
|
#define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
|
|
{
|
|
return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076
|
|
#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff
|
|
#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
|
|
{
|
|
return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077
|
|
#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003
|
|
#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
|
|
{
|
|
return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078
|
|
#define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
|
|
#define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
|
|
#define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
|
|
#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
|
|
#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
|
|
static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
|
|
{
|
|
return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
|
|
}
|
|
#define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
|
|
#define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000
|
|
|
|
#define REG_A4XX_GRAS_SC_CONTROL 0x0000207b
|
|
#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c
|
|
#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2
|
|
static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
|
|
{
|
|
return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
|
|
}
|
|
#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380
|
|
#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7
|
|
static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
|
|
}
|
|
#define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800
|
|
#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
|
|
#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
|
|
static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c
|
|
#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
|
|
#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
|
|
}
|
|
#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
|
|
#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
|
|
static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d
|
|
#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
|
|
#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
|
|
}
|
|
#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
|
|
#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
|
|
static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c
|
|
#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
|
|
#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
|
|
}
|
|
#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
|
|
#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
|
|
static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d
|
|
#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
|
|
#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
|
|
}
|
|
#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
|
|
#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
|
|
static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e
|
|
#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff
|
|
#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK;
|
|
}
|
|
#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000
|
|
#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16
|
|
static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f
|
|
#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff
|
|
#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0
|
|
static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK;
|
|
}
|
|
#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000
|
|
#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16
|
|
static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80
|
|
|
|
#define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83
|
|
|
|
#define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84
|
|
|
|
#define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88
|
|
|
|
#define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a
|
|
|
|
#define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b
|
|
|
|
#define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
|
|
|
|
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e
|
|
|
|
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f
|
|
|
|
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90
|
|
|
|
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91
|
|
|
|
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92
|
|
|
|
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93
|
|
|
|
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94
|
|
|
|
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
|
|
|
|
#define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
|
|
|
|
#define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04
|
|
|
|
#define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05
|
|
|
|
#define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
|
|
|
|
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06
|
|
|
|
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07
|
|
|
|
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08
|
|
|
|
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09
|
|
|
|
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a
|
|
|
|
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b
|
|
|
|
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c
|
|
|
|
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d
|
|
|
|
#define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
|
|
#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
|
|
#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
|
|
static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
|
|
}
|
|
#define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
|
|
#define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
|
|
#define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
|
|
#define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
|
|
#define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
|
|
#define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
|
|
static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
|
|
}
|
|
#define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
|
|
#define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
|
|
#define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
|
|
#define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
|
|
|
|
#define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1
|
|
#define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
|
|
#define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
|
|
static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
|
|
}
|
|
#define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
|
|
#define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
|
|
#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000
|
|
#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16
|
|
static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
|
|
}
|
|
#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000
|
|
#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24
|
|
static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2
|
|
#define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
|
|
#define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
|
|
static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
|
|
}
|
|
#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc
|
|
#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2
|
|
static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
|
|
}
|
|
#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00
|
|
#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10
|
|
static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
|
|
}
|
|
#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000
|
|
#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18
|
|
static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
|
|
#define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
|
|
#define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
|
|
static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4
|
|
|
|
#define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5
|
|
#define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
|
|
#define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
|
|
static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
|
|
}
|
|
#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
|
|
#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
|
|
static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
|
|
#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
|
|
#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
|
|
static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
#define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
|
|
#define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
|
|
static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6
|
|
#define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
|
|
#define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
|
|
static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
|
|
}
|
|
#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
|
|
#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
|
|
static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
|
|
#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
|
|
#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
|
|
static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
#define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
|
|
#define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
|
|
static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7
|
|
#define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
|
|
#define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0
|
|
static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
|
|
}
|
|
#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
|
|
#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
|
|
static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
|
|
#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
|
|
#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
|
|
static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
#define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
|
|
#define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24
|
|
static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8
|
|
#define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
|
|
#define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0
|
|
static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
|
|
}
|
|
#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
|
|
#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
|
|
static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
|
|
#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
|
|
#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
|
|
static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
#define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
|
|
#define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24
|
|
static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9
|
|
#define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
|
|
#define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0
|
|
static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
|
|
}
|
|
#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
|
|
#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
|
|
static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
|
|
}
|
|
#define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
|
|
#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
|
|
#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
|
|
static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
|
|
}
|
|
#define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
|
|
#define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24
|
|
static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_HLSQ_CS_CONTROL 0x000023ca
|
|
|
|
#define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd
|
|
|
|
#define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce
|
|
|
|
#define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf
|
|
|
|
#define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0
|
|
|
|
#define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1
|
|
|
|
#define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2
|
|
|
|
#define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
|
|
|
|
#define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
|
|
|
|
#define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
|
|
|
|
#define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6
|
|
|
|
#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7
|
|
|
|
#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8
|
|
|
|
#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9
|
|
|
|
#define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da
|
|
|
|
#define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db
|
|
|
|
#define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
|
|
#define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
|
|
|
|
#define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
|
|
|
|
#define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
|
|
|
|
#define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11
|
|
|
|
#define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12
|
|
|
|
#define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13
|
|
|
|
#define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14
|
|
|
|
#define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15
|
|
|
|
#define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16
|
|
|
|
#define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
|
|
|
|
#define REG_A4XX_PC_BIN_BASE 0x000021c0
|
|
|
|
#define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
|
|
#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
|
|
#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
|
|
static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
|
|
}
|
|
#define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
|
|
#define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
|
|
#define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
|
|
|
|
#define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5
|
|
#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007
|
|
#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0
|
|
static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
|
|
{
|
|
return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK;
|
|
}
|
|
#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038
|
|
#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3
|
|
static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
|
|
{
|
|
return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK;
|
|
}
|
|
#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040
|
|
|
|
#define REG_A4XX_PC_RESTART_INDEX 0x000021c6
|
|
|
|
#define REG_A4XX_PC_GS_PARAM 0x000021e5
|
|
#define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
|
|
#define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
|
|
static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
|
|
}
|
|
#define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
|
|
#define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
|
|
static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
|
|
}
|
|
#define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
|
|
#define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
|
|
static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
|
|
{
|
|
return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
|
|
}
|
|
#define A4XX_PC_GS_PARAM_LAYER 0x80000000
|
|
|
|
#define REG_A4XX_PC_HS_PARAM 0x000021e7
|
|
#define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
|
|
#define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
|
|
static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
|
|
}
|
|
#define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000
|
|
#define A4XX_PC_HS_PARAM_SPACING__SHIFT 21
|
|
static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
|
|
{
|
|
return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
|
|
}
|
|
#define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000
|
|
#define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23
|
|
static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
|
|
{
|
|
return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_VBIF_VERSION 0x00003000
|
|
|
|
#define REG_A4XX_VBIF_CLKON 0x00003001
|
|
#define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001
|
|
|
|
#define REG_A4XX_VBIF_ABIT_SORT 0x0000301c
|
|
|
|
#define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d
|
|
|
|
#define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
|
|
|
|
#define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
|
|
|
|
#define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
|
|
|
|
#define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030
|
|
|
|
#define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031
|
|
|
|
#define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
|
|
|
|
#define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
|
|
|
|
#define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
|
|
|
|
#define REG_A4XX_UNKNOWN_0D01 0x00000d01
|
|
|
|
#define REG_A4XX_UNKNOWN_0E42 0x00000e42
|
|
|
|
#define REG_A4XX_UNKNOWN_0EC2 0x00000ec2
|
|
|
|
#define REG_A4XX_UNKNOWN_2001 0x00002001
|
|
|
|
#define REG_A4XX_UNKNOWN_209B 0x0000209b
|
|
|
|
#define REG_A4XX_UNKNOWN_20EF 0x000020ef
|
|
|
|
#define REG_A4XX_UNKNOWN_2152 0x00002152
|
|
|
|
#define REG_A4XX_UNKNOWN_2153 0x00002153
|
|
|
|
#define REG_A4XX_UNKNOWN_2154 0x00002154
|
|
|
|
#define REG_A4XX_UNKNOWN_2155 0x00002155
|
|
|
|
#define REG_A4XX_UNKNOWN_2156 0x00002156
|
|
|
|
#define REG_A4XX_UNKNOWN_2157 0x00002157
|
|
|
|
#define REG_A4XX_UNKNOWN_21C3 0x000021c3
|
|
|
|
#define REG_A4XX_UNKNOWN_21E6 0x000021e6
|
|
|
|
#define REG_A4XX_UNKNOWN_2209 0x00002209
|
|
|
|
#define REG_A4XX_UNKNOWN_22D7 0x000022d7
|
|
|
|
#define REG_A4XX_UNKNOWN_2352 0x00002352
|
|
|
|
#define REG_A4XX_TEX_SAMP_0 0x00000000
|
|
#define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
|
|
#define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
|
|
#define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1
|
|
static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
|
|
{
|
|
return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK;
|
|
}
|
|
#define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
|
|
#define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3
|
|
static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
|
|
{
|
|
return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK;
|
|
}
|
|
#define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
|
|
#define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5
|
|
static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
|
|
{
|
|
return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK;
|
|
}
|
|
#define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
|
|
#define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8
|
|
static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
|
|
{
|
|
return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK;
|
|
}
|
|
#define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
|
|
#define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11
|
|
static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
|
|
{
|
|
return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
|
|
}
|
|
#define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
|
|
#define A4XX_TEX_SAMP_0_ANISO__SHIFT 14
|
|
static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
|
|
{
|
|
return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
|
|
}
|
|
#define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
|
|
#define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
|
|
static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val)
|
|
{
|
|
return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_TEX_SAMP_1 0x00000001
|
|
#define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
|
|
#define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
|
|
static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
|
|
{
|
|
return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
|
|
}
|
|
#define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
|
|
#define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
|
|
#define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
|
|
#define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
|
|
#define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
|
|
static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
|
|
{
|
|
return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
|
|
}
|
|
#define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
|
|
#define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
|
|
static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
|
|
{
|
|
return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_TEX_CONST_0 0x00000000
|
|
#define A4XX_TEX_CONST_0_TILED 0x00000001
|
|
#define A4XX_TEX_CONST_0_SRGB 0x00000004
|
|
#define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
|
|
#define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4
|
|
static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
|
|
{
|
|
return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK;
|
|
}
|
|
#define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
|
|
#define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
|
|
static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
|
|
{
|
|
return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK;
|
|
}
|
|
#define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
|
|
#define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
|
|
static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
|
|
{
|
|
return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK;
|
|
}
|
|
#define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
|
|
#define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13
|
|
static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
|
|
{
|
|
return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
|
|
}
|
|
#define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
|
|
#define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16
|
|
static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK;
|
|
}
|
|
#define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000
|
|
#define A4XX_TEX_CONST_0_FMT__SHIFT 22
|
|
static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
|
|
{
|
|
return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
|
|
}
|
|
#define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000
|
|
#define A4XX_TEX_CONST_0_TYPE__SHIFT 29
|
|
static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
|
|
{
|
|
return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_TEX_CONST_1 0x00000001
|
|
#define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff
|
|
#define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0
|
|
static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
|
|
}
|
|
#define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000
|
|
#define A4XX_TEX_CONST_1_WIDTH__SHIFT 15
|
|
static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_TEX_CONST_2 0x00000002
|
|
#define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
|
|
#define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
|
|
static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)
|
|
{
|
|
return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK;
|
|
}
|
|
#define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
|
|
#define A4XX_TEX_CONST_2_PITCH__SHIFT 9
|
|
static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK;
|
|
}
|
|
#define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000
|
|
#define A4XX_TEX_CONST_2_SWAP__SHIFT 30
|
|
static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_TEX_CONST_3 0x00000003
|
|
#define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff
|
|
#define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0
|
|
static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
|
|
{
|
|
return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
|
|
}
|
|
#define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000
|
|
#define A4XX_TEX_CONST_3_DEPTH__SHIFT 18
|
|
static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
|
|
{
|
|
return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_TEX_CONST_4 0x00000004
|
|
#define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f
|
|
#define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0
|
|
static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
|
|
{
|
|
return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
|
|
}
|
|
#define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0
|
|
#define A4XX_TEX_CONST_4_BASE__SHIFT 5
|
|
static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
|
|
}
|
|
|
|
#define REG_A4XX_TEX_CONST_5 0x00000005
|
|
|
|
#define REG_A4XX_TEX_CONST_6 0x00000006
|
|
|
|
#define REG_A4XX_TEX_CONST_7 0x00000007
|
|
|
|
|
|
#endif /* A4XX_XML */
|