200 lines
5.1 KiB
C
200 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/* Copyright (c) 2016-2017 Hisilicon Limited. */
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#ifndef __HCLGEVF_MAIN_H
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#define __HCLGEVF_MAIN_H
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#include <linux/fs.h>
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#include <linux/types.h>
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#include "hclge_mbx.h"
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#include "hclgevf_cmd.h"
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#include "hnae3.h"
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#define HCLGEVF_MOD_VERSION "v1.0"
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#define HCLGEVF_DRIVER_NAME "hclgevf"
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#define HCLGEVF_ROCEE_VECTOR_NUM 0
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#define HCLGEVF_MISC_VECTOR_NUM 0
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#define HCLGEVF_INVALID_VPORT 0xffff
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/* This number in actual depends upon the total number of VFs
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* created by physical function. But the maximum number of
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* possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}.
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*/
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#define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1)
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#define HCLGEVF_VECTOR_REG_BASE 0x20000
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#define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400
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#define HCLGEVF_VECTOR_REG_OFFSET 0x4
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#define HCLGEVF_VECTOR_VF_OFFSET 0x100000
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/* Vector0 interrupt CMDQ event source register(RW) */
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#define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100
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/* CMDQ register bits for RX event(=MBX event) */
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#define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1
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#define HCLGEVF_TQP_RESET_TRY_TIMES 10
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/* Reset related Registers */
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#define HCLGEVF_FUN_RST_ING 0x20C00
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#define HCLGEVF_FUN_RST_ING_B 0
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#define HCLGEVF_RSS_IND_TBL_SIZE 512
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#define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff
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#define HCLGEVF_RSS_KEY_SIZE 40
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#define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0
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#define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1
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#define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2
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#define HCLGEVF_RSS_HASH_ALGO_MASK 0xf
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#define HCLGEVF_RSS_CFG_TBL_NUM \
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(HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE)
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/* states of hclgevf device & tasks */
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enum hclgevf_states {
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/* device states */
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HCLGEVF_STATE_DOWN,
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HCLGEVF_STATE_DISABLED,
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/* task states */
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HCLGEVF_STATE_SERVICE_SCHED,
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HCLGEVF_STATE_RST_SERVICE_SCHED,
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HCLGEVF_STATE_RST_HANDLING,
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HCLGEVF_STATE_MBX_SERVICE_SCHED,
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HCLGEVF_STATE_MBX_HANDLING,
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};
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#define HCLGEVF_MPF_ENBALE 1
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struct hclgevf_mac {
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u8 mac_addr[ETH_ALEN];
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int link;
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u8 duplex;
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u32 speed;
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};
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struct hclgevf_hw {
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void __iomem *io_base;
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int num_vec;
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struct hclgevf_cmq cmq;
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struct hclgevf_mac mac;
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void *hdev; /* hchgevf device it is part of */
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};
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/* TQP stats */
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struct hlcgevf_tqp_stats {
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/* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */
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u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
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/* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */
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u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
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};
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struct hclgevf_tqp {
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struct device *dev; /* device for DMA mapping */
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struct hnae3_queue q;
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struct hlcgevf_tqp_stats tqp_stats;
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u16 index; /* global index in a NIC controller */
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bool alloced;
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};
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struct hclgevf_cfg {
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u8 vmdq_vport_num;
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u8 tc_num;
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u16 tqp_desc_num;
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u16 rx_buf_len;
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u8 phy_addr;
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u8 media_type;
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u8 mac_addr[ETH_ALEN];
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u32 numa_node_map;
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};
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struct hclgevf_rss_cfg {
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u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */
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u32 hash_algo;
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u32 rss_size;
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u8 hw_tc_map;
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u8 rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */
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};
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struct hclgevf_misc_vector {
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u8 __iomem *addr;
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int vector_irq;
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};
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struct hclgevf_dev {
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struct pci_dev *pdev;
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struct hnae3_ae_dev *ae_dev;
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struct hclgevf_hw hw;
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struct hclgevf_misc_vector misc_vector;
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struct hclgevf_rss_cfg rss_cfg;
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unsigned long state;
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#define HCLGEVF_RESET_REQUESTED 0
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#define HCLGEVF_RESET_PENDING 1
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unsigned long reset_state; /* requested, pending */
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u32 reset_attempts;
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u32 fw_version;
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u16 num_tqps; /* num task queue pairs of this PF */
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u16 alloc_rss_size; /* allocated RSS task queue */
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u16 rss_size_max; /* HW defined max RSS task queue */
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u16 num_alloc_vport; /* num vports this driver supports */
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u32 numa_node_mask;
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u16 rx_buf_len;
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u16 num_desc;
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u8 hw_tc_map;
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u16 num_msi;
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u16 num_msi_left;
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u16 num_msi_used;
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u32 base_msi_vector;
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u16 *vector_status;
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int *vector_irq;
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bool accept_mta_mc; /* whether to accept mta filter multicast */
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bool mbx_event_pending;
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struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */
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struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */
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struct timer_list service_timer;
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struct work_struct service_task;
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struct work_struct rst_service_task;
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struct work_struct mbx_service_task;
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struct hclgevf_tqp *htqp;
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struct hnae3_handle nic;
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struct hnae3_handle roce;
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struct hnae3_client *nic_client;
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struct hnae3_client *roce_client;
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u32 flag;
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};
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static inline bool hclgevf_dev_ongoing_reset(struct hclgevf_dev *hdev)
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{
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return (hdev &&
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(test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) &&
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(hdev->nic.reset_level == HNAE3_VF_RESET));
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}
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static inline bool hclgevf_dev_ongoing_full_reset(struct hclgevf_dev *hdev)
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{
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return (hdev &&
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(test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) &&
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(hdev->nic.reset_level == HNAE3_VF_FULL_RESET));
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}
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int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode,
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const u8 *msg_data, u8 msg_len, bool need_resp,
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u8 *resp_data, u16 resp_len);
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void hclgevf_mbx_handler(struct hclgevf_dev *hdev);
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void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev);
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void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state);
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void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
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u8 duplex);
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void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev);
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void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev);
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#endif
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