638 lines
16 KiB
C
638 lines
16 KiB
C
/*
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* Copyright (c) 2006 QLogic, Inc. All rights reserved.
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* Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/vmalloc.h>
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#include "ipath_kernel.h"
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/*
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* InfiniPath I2C driver for a serial eeprom. This is not a generic
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* I2C interface. For a start, the device we're using (Atmel AT24C11)
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* doesn't work like a regular I2C device. It looks like one
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* electrically, but not logically. Normal I2C devices have a single
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* 7-bit or 10-bit I2C address that they respond to. Valid 7-bit
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* addresses range from 0x03 to 0x77. Addresses 0x00 to 0x02 and 0x78
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* to 0x7F are special reserved addresses (e.g. 0x00 is the "general
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* call" address.) The Atmel device, on the other hand, responds to ALL
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* 7-bit addresses. It's designed to be the only device on a given I2C
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* bus. A 7-bit address corresponds to the memory address within the
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* Atmel device itself.
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*
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* Also, the timing requirements mean more than simple software
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* bitbanging, with readbacks from chip to ensure timing (simple udelay
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* is not enough).
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*
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* This all means that accessing the device is specialized enough
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* that using the standard kernel I2C bitbanging interface would be
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* impossible. For example, the core I2C eeprom driver expects to find
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* a device at one or more of a limited set of addresses only. It doesn't
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* allow writing to an eeprom. It also doesn't provide any means of
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* accessing eeprom contents from within the kernel, only via sysfs.
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*/
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enum i2c_type {
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i2c_line_scl = 0,
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i2c_line_sda
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};
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enum i2c_state {
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i2c_line_low = 0,
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i2c_line_high
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};
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#define READ_CMD 1
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#define WRITE_CMD 0
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static int eeprom_init;
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/*
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* The gpioval manipulation really should be protected by spinlocks
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* or be converted to use atomic operations.
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*/
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/**
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* i2c_gpio_set - set a GPIO line
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* @dd: the infinipath device
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* @line: the line to set
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* @new_line_state: the state to set
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*
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* Returns 0 if the line was set to the new state successfully, non-zero
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* on error.
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*/
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static int i2c_gpio_set(struct ipath_devdata *dd,
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enum i2c_type line,
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enum i2c_state new_line_state)
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{
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u64 read_val, write_val, mask, *gpioval;
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gpioval = &dd->ipath_gpio_out;
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read_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extctrl);
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if (line == i2c_line_scl)
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mask = dd->ipath_gpio_scl;
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else
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mask = dd->ipath_gpio_sda;
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if (new_line_state == i2c_line_high)
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/* tri-state the output rather than force high */
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write_val = read_val & ~mask;
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else
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/* config line to be an output */
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write_val = read_val | mask;
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ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, write_val);
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/* set high and verify */
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if (new_line_state == i2c_line_high)
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write_val = 0x1UL;
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else
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write_val = 0x0UL;
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if (line == i2c_line_scl) {
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write_val <<= dd->ipath_gpio_scl_num;
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*gpioval = *gpioval & ~(1UL << dd->ipath_gpio_scl_num);
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*gpioval |= write_val;
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} else {
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write_val <<= dd->ipath_gpio_sda_num;
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*gpioval = *gpioval & ~(1UL << dd->ipath_gpio_sda_num);
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*gpioval |= write_val;
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}
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ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_out, *gpioval);
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return 0;
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}
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/**
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* i2c_gpio_get - get a GPIO line state
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* @dd: the infinipath device
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* @line: the line to get
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* @curr_statep: where to put the line state
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*
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* Returns 0 if the line was set to the new state successfully, non-zero
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* on error. curr_state is not set on error.
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*/
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static int i2c_gpio_get(struct ipath_devdata *dd,
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enum i2c_type line,
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enum i2c_state *curr_statep)
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{
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u64 read_val, write_val, mask;
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int ret;
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/* check args */
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if (curr_statep == NULL) {
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ret = 1;
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goto bail;
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}
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read_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extctrl);
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/* config line to be an input */
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if (line == i2c_line_scl)
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mask = dd->ipath_gpio_scl;
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else
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mask = dd->ipath_gpio_sda;
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write_val = read_val & ~mask;
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ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, write_val);
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read_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
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if (read_val & mask)
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*curr_statep = i2c_line_high;
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else
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*curr_statep = i2c_line_low;
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ret = 0;
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bail:
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return ret;
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}
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/**
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* i2c_wait_for_writes - wait for a write
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* @dd: the infinipath device
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*
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* We use this instead of udelay directly, so we can make sure
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* that previous register writes have been flushed all the way
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* to the chip. Since we are delaying anyway, the cost doesn't
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* hurt, and makes the bit twiddling more regular
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*/
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static void i2c_wait_for_writes(struct ipath_devdata *dd)
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{
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(void)ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
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rmb();
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}
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static void scl_out(struct ipath_devdata *dd, u8 bit)
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{
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i2c_gpio_set(dd, i2c_line_scl, bit ? i2c_line_high : i2c_line_low);
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i2c_wait_for_writes(dd);
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}
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static void sda_out(struct ipath_devdata *dd, u8 bit)
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{
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i2c_gpio_set(dd, i2c_line_sda, bit ? i2c_line_high : i2c_line_low);
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i2c_wait_for_writes(dd);
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}
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static u8 sda_in(struct ipath_devdata *dd, int wait)
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{
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enum i2c_state bit;
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if (i2c_gpio_get(dd, i2c_line_sda, &bit))
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ipath_dbg("get bit failed!\n");
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if (wait)
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i2c_wait_for_writes(dd);
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return bit == i2c_line_high ? 1U : 0;
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}
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/**
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* i2c_ackrcv - see if ack following write is true
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* @dd: the infinipath device
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*/
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static int i2c_ackrcv(struct ipath_devdata *dd)
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{
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u8 ack_received;
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/* AT ENTRY SCL = LOW */
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/* change direction, ignore data */
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ack_received = sda_in(dd, 1);
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scl_out(dd, i2c_line_high);
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ack_received = sda_in(dd, 1) == 0;
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scl_out(dd, i2c_line_low);
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return ack_received;
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}
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/**
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* wr_byte - write a byte, one bit at a time
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* @dd: the infinipath device
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* @data: the byte to write
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*
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* Returns 0 if we got the following ack, otherwise 1
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*/
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static int wr_byte(struct ipath_devdata *dd, u8 data)
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{
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int bit_cntr;
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u8 bit;
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for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) {
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bit = (data >> bit_cntr) & 1;
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sda_out(dd, bit);
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scl_out(dd, i2c_line_high);
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scl_out(dd, i2c_line_low);
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}
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return (!i2c_ackrcv(dd)) ? 1 : 0;
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}
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static void send_ack(struct ipath_devdata *dd)
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{
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sda_out(dd, i2c_line_low);
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scl_out(dd, i2c_line_high);
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scl_out(dd, i2c_line_low);
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sda_out(dd, i2c_line_high);
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}
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/**
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* i2c_startcmd - transmit the start condition, followed by address/cmd
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* @dd: the infinipath device
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* @offset_dir: direction byte
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*
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* (both clock/data high, clock high, data low while clock is high)
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*/
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static int i2c_startcmd(struct ipath_devdata *dd, u8 offset_dir)
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{
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int res;
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/* issue start sequence */
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sda_out(dd, i2c_line_high);
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scl_out(dd, i2c_line_high);
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sda_out(dd, i2c_line_low);
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scl_out(dd, i2c_line_low);
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/* issue length and direction byte */
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res = wr_byte(dd, offset_dir);
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if (res)
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ipath_cdbg(VERBOSE, "No ack to complete start\n");
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return res;
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}
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/**
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* stop_cmd - transmit the stop condition
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* @dd: the infinipath device
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*
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* (both clock/data low, clock high, data high while clock is high)
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*/
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static void stop_cmd(struct ipath_devdata *dd)
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{
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scl_out(dd, i2c_line_low);
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sda_out(dd, i2c_line_low);
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scl_out(dd, i2c_line_high);
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sda_out(dd, i2c_line_high);
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udelay(2);
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}
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/**
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* eeprom_reset - reset I2C communication
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* @dd: the infinipath device
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*/
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static int eeprom_reset(struct ipath_devdata *dd)
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{
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int clock_cycles_left = 9;
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u64 *gpioval = &dd->ipath_gpio_out;
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int ret;
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eeprom_init = 1;
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*gpioval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_gpio_out);
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ipath_cdbg(VERBOSE, "Resetting i2c eeprom; initial gpioout reg "
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"is %llx\n", (unsigned long long) *gpioval);
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/*
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* This is to get the i2c into a known state, by first going low,
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* then tristate sda (and then tristate scl as first thing
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* in loop)
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*/
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scl_out(dd, i2c_line_low);
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sda_out(dd, i2c_line_high);
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while (clock_cycles_left--) {
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scl_out(dd, i2c_line_high);
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if (sda_in(dd, 0)) {
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sda_out(dd, i2c_line_low);
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scl_out(dd, i2c_line_low);
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ret = 0;
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goto bail;
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}
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scl_out(dd, i2c_line_low);
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}
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ret = 1;
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bail:
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return ret;
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}
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/**
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* ipath_eeprom_read - receives bytes from the eeprom via I2C
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* @dd: the infinipath device
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* @eeprom_offset: address to read from
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* @buffer: where to store result
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* @len: number of bytes to receive
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*/
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int ipath_eeprom_read(struct ipath_devdata *dd, u8 eeprom_offset,
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void *buffer, int len)
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{
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/* compiler complains unless initialized */
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u8 single_byte = 0;
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int bit_cntr;
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int ret;
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if (!eeprom_init)
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eeprom_reset(dd);
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eeprom_offset = (eeprom_offset << 1) | READ_CMD;
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if (i2c_startcmd(dd, eeprom_offset)) {
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ipath_dbg("Failed startcmd\n");
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stop_cmd(dd);
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ret = 1;
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goto bail;
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}
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/*
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* eeprom keeps clocking data out as long as we ack, automatically
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* incrementing the address.
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*/
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while (len-- > 0) {
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/* get data */
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single_byte = 0;
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for (bit_cntr = 8; bit_cntr; bit_cntr--) {
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u8 bit;
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scl_out(dd, i2c_line_high);
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bit = sda_in(dd, 0);
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single_byte |= bit << (bit_cntr - 1);
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scl_out(dd, i2c_line_low);
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}
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/* send ack if not the last byte */
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if (len)
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send_ack(dd);
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*((u8 *) buffer) = single_byte;
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buffer++;
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}
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stop_cmd(dd);
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ret = 0;
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bail:
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return ret;
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}
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/**
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* ipath_eeprom_write - writes data to the eeprom via I2C
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* @dd: the infinipath device
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* @eeprom_offset: where to place data
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* @buffer: data to write
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* @len: number of bytes to write
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*/
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int ipath_eeprom_write(struct ipath_devdata *dd, u8 eeprom_offset,
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const void *buffer, int len)
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{
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u8 single_byte;
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int sub_len;
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const u8 *bp = buffer;
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int max_wait_time, i;
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int ret;
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if (!eeprom_init)
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eeprom_reset(dd);
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while (len > 0) {
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if (i2c_startcmd(dd, (eeprom_offset << 1) | WRITE_CMD)) {
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ipath_dbg("Failed to start cmd offset %u\n",
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eeprom_offset);
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goto failed_write;
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}
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sub_len = min(len, 4);
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eeprom_offset += sub_len;
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len -= sub_len;
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for (i = 0; i < sub_len; i++) {
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if (wr_byte(dd, *bp++)) {
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ipath_dbg("no ack after byte %u/%u (%u "
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"total remain)\n", i, sub_len,
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len + sub_len - i);
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goto failed_write;
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}
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}
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stop_cmd(dd);
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/*
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* wait for write complete by waiting for a successful
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* read (the chip replies with a zero after the write
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* cmd completes, and before it writes to the eeprom.
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* The startcmd for the read will fail the ack until
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* the writes have completed. We do this inline to avoid
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* the debug prints that are in the real read routine
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* if the startcmd fails.
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*/
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max_wait_time = 100;
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while (i2c_startcmd(dd, READ_CMD)) {
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stop_cmd(dd);
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if (!--max_wait_time) {
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ipath_dbg("Did not get successful read to "
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"complete write\n");
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goto failed_write;
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}
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}
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/* now read the zero byte */
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for (i = single_byte = 0; i < 8; i++) {
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u8 bit;
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scl_out(dd, i2c_line_high);
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bit = sda_in(dd, 0);
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scl_out(dd, i2c_line_low);
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single_byte <<= 1;
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single_byte |= bit;
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}
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stop_cmd(dd);
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}
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ret = 0;
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goto bail;
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failed_write:
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stop_cmd(dd);
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ret = 1;
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bail:
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return ret;
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}
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static u8 flash_csum(struct ipath_flash *ifp, int adjust)
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{
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u8 *ip = (u8 *) ifp;
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u8 csum = 0, len;
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for (len = 0; len < ifp->if_length; len++)
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csum += *ip++;
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csum -= ifp->if_csum;
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csum = ~csum;
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if (adjust)
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ifp->if_csum = csum;
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return csum;
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}
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/**
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* ipath_get_guid - get the GUID from the i2c device
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* @dd: the infinipath device
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*
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* We have the capability to use the ipath_nguid field, and get
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* the guid from the first chip's flash, to use for all of them.
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*/
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void ipath_get_eeprom_info(struct ipath_devdata *dd)
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{
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void *buf;
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struct ipath_flash *ifp;
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__be64 guid;
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int len;
|
|
u8 csum, *bguid;
|
|
int t = dd->ipath_unit;
|
|
struct ipath_devdata *dd0 = ipath_lookup(0);
|
|
|
|
if (t && dd0->ipath_nguid > 1 && t <= dd0->ipath_nguid) {
|
|
u8 *bguid, oguid;
|
|
dd->ipath_guid = dd0->ipath_guid;
|
|
bguid = (u8 *) & dd->ipath_guid;
|
|
|
|
oguid = bguid[7];
|
|
bguid[7] += t;
|
|
if (oguid > bguid[7]) {
|
|
if (bguid[6] == 0xff) {
|
|
if (bguid[5] == 0xff) {
|
|
ipath_dev_err(
|
|
dd,
|
|
"Can't set %s GUID from "
|
|
"base, wraps to OUI!\n",
|
|
ipath_get_unit_name(t));
|
|
dd->ipath_guid = 0;
|
|
goto bail;
|
|
}
|
|
bguid[5]++;
|
|
}
|
|
bguid[6]++;
|
|
}
|
|
dd->ipath_nguid = 1;
|
|
|
|
ipath_dbg("nguid %u, so adding %u to device 0 guid, "
|
|
"for %llx\n",
|
|
dd0->ipath_nguid, t,
|
|
(unsigned long long) be64_to_cpu(dd->ipath_guid));
|
|
goto bail;
|
|
}
|
|
|
|
len = offsetof(struct ipath_flash, if_future);
|
|
buf = vmalloc(len);
|
|
if (!buf) {
|
|
ipath_dev_err(dd, "Couldn't allocate memory to read %u "
|
|
"bytes from eeprom for GUID\n", len);
|
|
goto bail;
|
|
}
|
|
|
|
if (ipath_eeprom_read(dd, 0, buf, len)) {
|
|
ipath_dev_err(dd, "Failed reading GUID from eeprom\n");
|
|
goto done;
|
|
}
|
|
ifp = (struct ipath_flash *)buf;
|
|
|
|
csum = flash_csum(ifp, 0);
|
|
if (csum != ifp->if_csum) {
|
|
dev_info(&dd->pcidev->dev, "Bad I2C flash checksum: "
|
|
"0x%x, not 0x%x\n", csum, ifp->if_csum);
|
|
goto done;
|
|
}
|
|
if (*(__be64 *) ifp->if_guid == 0ULL ||
|
|
*(__be64 *) ifp->if_guid == __constant_cpu_to_be64(-1LL)) {
|
|
ipath_dev_err(dd, "Invalid GUID %llx from flash; "
|
|
"ignoring\n",
|
|
*(unsigned long long *) ifp->if_guid);
|
|
/* don't allow GUID if all 0 or all 1's */
|
|
goto done;
|
|
}
|
|
|
|
/* complain, but allow it */
|
|
if (*(u64 *) ifp->if_guid == 0x100007511000000ULL)
|
|
dev_info(&dd->pcidev->dev, "Warning, GUID %llx is "
|
|
"default, probably not correct!\n",
|
|
*(unsigned long long *) ifp->if_guid);
|
|
|
|
bguid = ifp->if_guid;
|
|
if (!bguid[0] && !bguid[1] && !bguid[2]) {
|
|
/* original incorrect GUID format in flash; fix in
|
|
* core copy, by shifting up 2 octets; don't need to
|
|
* change top octet, since both it and shifted are
|
|
* 0.. */
|
|
bguid[1] = bguid[3];
|
|
bguid[2] = bguid[4];
|
|
bguid[3] = bguid[4] = 0;
|
|
guid = *(__be64 *) ifp->if_guid;
|
|
ipath_cdbg(VERBOSE, "Old GUID format in flash, top 3 zero, "
|
|
"shifting 2 octets\n");
|
|
} else
|
|
guid = *(__be64 *) ifp->if_guid;
|
|
dd->ipath_guid = guid;
|
|
dd->ipath_nguid = ifp->if_numguid;
|
|
/*
|
|
* Things are slightly complicated by the desire to transparently
|
|
* support both the Pathscale 10-digit serial number and the QLogic
|
|
* 13-character version.
|
|
*/
|
|
if ((ifp->if_fversion > 1) && ifp->if_sprefix[0]
|
|
&& ((u8 *)ifp->if_sprefix)[0] != 0xFF) {
|
|
/* This board has a Serial-prefix, which is stored
|
|
* elsewhere for backward-compatibility.
|
|
*/
|
|
char *snp = dd->ipath_serial;
|
|
int len;
|
|
memcpy(snp, ifp->if_sprefix, sizeof ifp->if_sprefix);
|
|
snp[sizeof ifp->if_sprefix] = '\0';
|
|
len = strlen(snp);
|
|
snp += len;
|
|
len = (sizeof dd->ipath_serial) - len;
|
|
if (len > sizeof ifp->if_serial) {
|
|
len = sizeof ifp->if_serial;
|
|
}
|
|
memcpy(snp, ifp->if_serial, len);
|
|
} else
|
|
memcpy(dd->ipath_serial, ifp->if_serial,
|
|
sizeof ifp->if_serial);
|
|
|
|
ipath_cdbg(VERBOSE, "Initted GUID to %llx from eeprom\n",
|
|
(unsigned long long) be64_to_cpu(dd->ipath_guid));
|
|
|
|
done:
|
|
vfree(buf);
|
|
|
|
bail:;
|
|
}
|