471 lines
12 KiB
C
471 lines
12 KiB
C
/*
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* Copyright (C) 2012 Red Hat
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*
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* based in parts on udlfb.c:
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* Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it>
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* Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com>
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* Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
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* This file is subject to the terms and conditions of the GNU General Public
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* License v2. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_plane_helper.h>
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#include "udl_drv.h"
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/*
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* All DisplayLink bulk operations start with 0xAF, followed by specific code
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* All operations are written to buffers which then later get sent to device
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*/
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static char *udl_set_register(char *buf, u8 reg, u8 val)
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{
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*buf++ = 0xAF;
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*buf++ = 0x20;
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*buf++ = reg;
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*buf++ = val;
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return buf;
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}
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static char *udl_vidreg_lock(char *buf)
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{
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return udl_set_register(buf, 0xFF, 0x00);
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}
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static char *udl_vidreg_unlock(char *buf)
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{
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return udl_set_register(buf, 0xFF, 0xFF);
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}
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/*
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* On/Off for driving the DisplayLink framebuffer to the display
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* 0x00 H and V sync on
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* 0x01 H and V sync off (screen blank but powered)
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* 0x07 DPMS powerdown (requires modeset to come back)
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*/
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static char *udl_set_blank(char *buf, int dpms_mode)
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{
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u8 reg;
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switch (dpms_mode) {
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case DRM_MODE_DPMS_OFF:
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reg = 0x07;
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break;
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case DRM_MODE_DPMS_STANDBY:
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reg = 0x05;
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break;
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case DRM_MODE_DPMS_SUSPEND:
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reg = 0x01;
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break;
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case DRM_MODE_DPMS_ON:
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reg = 0x00;
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break;
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}
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return udl_set_register(buf, 0x1f, reg);
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}
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static char *udl_set_color_depth(char *buf, u8 selection)
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{
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return udl_set_register(buf, 0x00, selection);
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}
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static char *udl_set_base16bpp(char *wrptr, u32 base)
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{
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/* the base pointer is 16 bits wide, 0x20 is hi byte. */
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wrptr = udl_set_register(wrptr, 0x20, base >> 16);
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wrptr = udl_set_register(wrptr, 0x21, base >> 8);
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return udl_set_register(wrptr, 0x22, base);
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}
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/*
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* DisplayLink HW has separate 16bpp and 8bpp framebuffers.
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* In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer
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*/
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static char *udl_set_base8bpp(char *wrptr, u32 base)
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{
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wrptr = udl_set_register(wrptr, 0x26, base >> 16);
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wrptr = udl_set_register(wrptr, 0x27, base >> 8);
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return udl_set_register(wrptr, 0x28, base);
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}
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static char *udl_set_register_16(char *wrptr, u8 reg, u16 value)
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{
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wrptr = udl_set_register(wrptr, reg, value >> 8);
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return udl_set_register(wrptr, reg+1, value);
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}
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/*
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* This is kind of weird because the controller takes some
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* register values in a different byte order than other registers.
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*/
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static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value)
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{
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wrptr = udl_set_register(wrptr, reg, value);
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return udl_set_register(wrptr, reg+1, value >> 8);
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}
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/*
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* LFSR is linear feedback shift register. The reason we have this is
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* because the display controller needs to minimize the clock depth of
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* various counters used in the display path. So this code reverses the
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* provided value into the lfsr16 value by counting backwards to get
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* the value that needs to be set in the hardware comparator to get the
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* same actual count. This makes sense once you read above a couple of
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* times and think about it from a hardware perspective.
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*/
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static u16 udl_lfsr16(u16 actual_count)
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{
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u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */
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while (actual_count--) {
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lv = ((lv << 1) |
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(((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1))
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& 0xFFFF;
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}
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return (u16) lv;
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}
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/*
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* This does LFSR conversion on the value that is to be written.
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* See LFSR explanation above for more detail.
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*/
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static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value)
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{
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return udl_set_register_16(wrptr, reg, udl_lfsr16(value));
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}
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/*
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* This takes a standard fbdev screeninfo struct and all of its monitor mode
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* details and converts them into the DisplayLink equivalent register commands.
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ERR(vreg(dev, 0x00, (color_depth == 16) ? 0 : 1));
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ERR(vreg_lfsr16(dev, 0x01, xDisplayStart));
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ERR(vreg_lfsr16(dev, 0x03, xDisplayEnd));
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ERR(vreg_lfsr16(dev, 0x05, yDisplayStart));
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ERR(vreg_lfsr16(dev, 0x07, yDisplayEnd));
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ERR(vreg_lfsr16(dev, 0x09, xEndCount));
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ERR(vreg_lfsr16(dev, 0x0B, hSyncStart));
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ERR(vreg_lfsr16(dev, 0x0D, hSyncEnd));
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ERR(vreg_big_endian(dev, 0x0F, hPixels));
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ERR(vreg_lfsr16(dev, 0x11, yEndCount));
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ERR(vreg_lfsr16(dev, 0x13, vSyncStart));
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ERR(vreg_lfsr16(dev, 0x15, vSyncEnd));
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ERR(vreg_big_endian(dev, 0x17, vPixels));
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ERR(vreg_little_endian(dev, 0x1B, pixelClock5KHz));
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ERR(vreg(dev, 0x1F, 0));
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ERR(vbuf(dev, WRITE_VIDREG_UNLOCK, DSIZEOF(WRITE_VIDREG_UNLOCK)));
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*/
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static char *udl_set_vid_cmds(char *wrptr, struct drm_display_mode *mode)
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{
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u16 xds, yds;
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u16 xde, yde;
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u16 yec;
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/* x display start */
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xds = mode->crtc_htotal - mode->crtc_hsync_start;
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wrptr = udl_set_register_lfsr16(wrptr, 0x01, xds);
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/* x display end */
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xde = xds + mode->crtc_hdisplay;
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wrptr = udl_set_register_lfsr16(wrptr, 0x03, xde);
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/* y display start */
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yds = mode->crtc_vtotal - mode->crtc_vsync_start;
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wrptr = udl_set_register_lfsr16(wrptr, 0x05, yds);
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/* y display end */
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yde = yds + mode->crtc_vdisplay;
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wrptr = udl_set_register_lfsr16(wrptr, 0x07, yde);
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/* x end count is active + blanking - 1 */
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wrptr = udl_set_register_lfsr16(wrptr, 0x09,
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mode->crtc_htotal - 1);
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/* libdlo hardcodes hsync start to 1 */
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wrptr = udl_set_register_lfsr16(wrptr, 0x0B, 1);
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/* hsync end is width of sync pulse + 1 */
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wrptr = udl_set_register_lfsr16(wrptr, 0x0D,
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mode->crtc_hsync_end - mode->crtc_hsync_start + 1);
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/* hpixels is active pixels */
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wrptr = udl_set_register_16(wrptr, 0x0F, mode->hdisplay);
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/* yendcount is vertical active + vertical blanking */
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yec = mode->crtc_vtotal;
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wrptr = udl_set_register_lfsr16(wrptr, 0x11, yec);
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/* libdlo hardcodes vsync start to 0 */
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wrptr = udl_set_register_lfsr16(wrptr, 0x13, 0);
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/* vsync end is width of vsync pulse */
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wrptr = udl_set_register_lfsr16(wrptr, 0x15, mode->crtc_vsync_end - mode->crtc_vsync_start);
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/* vpixels is active pixels */
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wrptr = udl_set_register_16(wrptr, 0x17, mode->crtc_vdisplay);
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wrptr = udl_set_register_16be(wrptr, 0x1B,
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mode->clock / 5);
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return wrptr;
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}
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static char *udl_dummy_render(char *wrptr)
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{
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*wrptr++ = 0xAF;
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*wrptr++ = 0x6A; /* copy */
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*wrptr++ = 0x00; /* from addr */
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*wrptr++ = 0x00;
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*wrptr++ = 0x00;
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*wrptr++ = 0x01; /* one pixel */
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*wrptr++ = 0x00; /* to address */
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*wrptr++ = 0x00;
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*wrptr++ = 0x00;
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return wrptr;
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}
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static int udl_crtc_write_mode_to_hw(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct udl_device *udl = dev->dev_private;
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struct urb *urb;
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char *buf;
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int retval;
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urb = udl_get_urb(dev);
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if (!urb)
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return -ENOMEM;
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buf = (char *)urb->transfer_buffer;
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memcpy(buf, udl->mode_buf, udl->mode_buf_len);
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retval = udl_submit_urb(dev, urb, udl->mode_buf_len);
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DRM_INFO("write mode info %d\n", udl->mode_buf_len);
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return retval;
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}
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static void udl_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
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struct drm_device *dev = crtc->dev;
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struct udl_device *udl = dev->dev_private;
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int retval;
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if (mode == DRM_MODE_DPMS_OFF) {
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char *buf;
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struct urb *urb;
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urb = udl_get_urb(dev);
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if (!urb)
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return;
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buf = (char *)urb->transfer_buffer;
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buf = udl_vidreg_lock(buf);
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buf = udl_set_blank(buf, mode);
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buf = udl_vidreg_unlock(buf);
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buf = udl_dummy_render(buf);
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retval = udl_submit_urb(dev, urb, buf - (char *)
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urb->transfer_buffer);
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} else {
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if (udl->mode_buf_len == 0) {
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DRM_ERROR("Trying to enable DPMS with no mode\n");
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return;
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}
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udl_crtc_write_mode_to_hw(crtc);
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}
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}
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#if 0
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static int
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udl_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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int x, int y, enum mode_set_atomic state)
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{
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return 0;
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}
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static int
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udl_pipe_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb)
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{
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return 0;
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}
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#endif
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static int udl_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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int x, int y,
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struct drm_framebuffer *old_fb)
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{
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struct drm_device *dev = crtc->dev;
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struct udl_framebuffer *ufb = to_udl_fb(crtc->primary->fb);
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struct udl_device *udl = dev->dev_private;
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char *buf;
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char *wrptr;
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int color_depth = 0;
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udl->crtc = crtc;
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buf = (char *)udl->mode_buf;
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/* for now we just clip 24 -> 16 - if we fix that fix this */
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/*if (crtc->fb->bits_per_pixel != 16)
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color_depth = 1; */
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/* This first section has to do with setting the base address on the
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* controller * associated with the display. There are 2 base
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* pointers, currently, we only * use the 16 bpp segment.
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*/
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wrptr = udl_vidreg_lock(buf);
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wrptr = udl_set_color_depth(wrptr, color_depth);
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/* set base for 16bpp segment to 0 */
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wrptr = udl_set_base16bpp(wrptr, 0);
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/* set base for 8bpp segment to end of fb */
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wrptr = udl_set_base8bpp(wrptr, 2 * mode->vdisplay * mode->hdisplay);
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wrptr = udl_set_vid_cmds(wrptr, adjusted_mode);
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wrptr = udl_set_blank(wrptr, DRM_MODE_DPMS_ON);
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wrptr = udl_vidreg_unlock(wrptr);
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wrptr = udl_dummy_render(wrptr);
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if (old_fb) {
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struct udl_framebuffer *uold_fb = to_udl_fb(old_fb);
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uold_fb->active_16 = false;
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}
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ufb->active_16 = true;
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udl->mode_buf_len = wrptr - buf;
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/* damage all of it */
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udl_handle_damage(ufb, 0, 0, ufb->base.width, ufb->base.height);
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return 0;
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}
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static void udl_crtc_disable(struct drm_crtc *crtc)
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{
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udl_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
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}
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static void udl_crtc_destroy(struct drm_crtc *crtc)
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{
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drm_crtc_cleanup(crtc);
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kfree(crtc);
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}
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static int udl_crtc_page_flip(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_pending_vblank_event *event,
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uint32_t page_flip_flags)
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{
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struct udl_framebuffer *ufb = to_udl_fb(fb);
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struct drm_device *dev = crtc->dev;
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unsigned long flags;
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struct drm_framebuffer *old_fb = crtc->primary->fb;
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if (old_fb) {
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struct udl_framebuffer *uold_fb = to_udl_fb(old_fb);
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uold_fb->active_16 = false;
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}
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ufb->active_16 = true;
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udl_handle_damage(ufb, 0, 0, fb->width, fb->height);
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spin_lock_irqsave(&dev->event_lock, flags);
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if (event)
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drm_crtc_send_vblank_event(crtc, event);
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spin_unlock_irqrestore(&dev->event_lock, flags);
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crtc->primary->fb = fb;
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return 0;
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}
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static void udl_crtc_prepare(struct drm_crtc *crtc)
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{
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}
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static void udl_crtc_commit(struct drm_crtc *crtc)
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{
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udl_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
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}
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static const struct drm_crtc_helper_funcs udl_helper_funcs = {
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.dpms = udl_crtc_dpms,
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.mode_set = udl_crtc_mode_set,
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.prepare = udl_crtc_prepare,
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.commit = udl_crtc_commit,
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.disable = udl_crtc_disable,
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};
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static const struct drm_crtc_funcs udl_crtc_funcs = {
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.set_config = drm_crtc_helper_set_config,
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.destroy = udl_crtc_destroy,
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.page_flip = udl_crtc_page_flip,
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};
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static int udl_crtc_init(struct drm_device *dev)
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{
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struct drm_crtc *crtc;
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crtc = kzalloc(sizeof(struct drm_crtc) + sizeof(struct drm_connector *), GFP_KERNEL);
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if (crtc == NULL)
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return -ENOMEM;
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drm_crtc_init(dev, crtc, &udl_crtc_funcs);
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drm_crtc_helper_add(crtc, &udl_helper_funcs);
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return 0;
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}
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static const struct drm_mode_config_funcs udl_mode_funcs = {
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.fb_create = udl_fb_user_fb_create,
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.output_poll_changed = NULL,
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};
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int udl_modeset_init(struct drm_device *dev)
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{
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struct drm_encoder *encoder;
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drm_mode_config_init(dev);
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dev->mode_config.min_width = 640;
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dev->mode_config.min_height = 480;
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dev->mode_config.max_width = 2048;
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dev->mode_config.max_height = 2048;
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dev->mode_config.prefer_shadow = 0;
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dev->mode_config.preferred_depth = 24;
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dev->mode_config.funcs = &udl_mode_funcs;
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udl_crtc_init(dev);
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encoder = udl_encoder_init(dev);
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udl_connector_init(dev, encoder);
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return 0;
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}
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void udl_modeset_restore(struct drm_device *dev)
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{
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struct udl_device *udl = dev->dev_private;
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struct udl_framebuffer *ufb;
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if (!udl->crtc || !udl->crtc->primary->fb)
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return;
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udl_crtc_commit(udl->crtc);
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ufb = to_udl_fb(udl->crtc->primary->fb);
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udl_handle_damage(ufb, 0, 0, ufb->base.width, ufb->base.height);
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}
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void udl_modeset_cleanup(struct drm_device *dev)
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{
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drm_mode_config_cleanup(dev);
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}
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