90 lines
3.4 KiB
C
90 lines
3.4 KiB
C
/*
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* Copyright © 2014-2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef _INTEL_GUC_SUBMISSION_H_
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#define _INTEL_GUC_SUBMISSION_H_
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#include <linux/spinlock.h>
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#include "gt/intel_engine_types.h"
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#include "i915_gem.h"
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#include "i915_selftest.h"
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struct drm_i915_private;
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/*
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* This structure primarily describes the GEM object shared with the GuC.
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* The specs sometimes refer to this object as a "GuC context", but we use
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* the term "client" to avoid confusion with hardware contexts. This
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* GEM object is held for the entire lifetime of our interaction with
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* the GuC, being allocated before the GuC is loaded with its firmware.
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* Because there's no way to update the address used by the GuC after
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* initialisation, the shared object must stay pinned into the GGTT as
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* long as the GuC is in use. We also keep the first page (only) mapped
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* into kernel address space, as it includes shared data that must be
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* updated on every request submission.
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*
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* The single GEM object described here is actually made up of several
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* separate areas, as far as the GuC is concerned. The first page (kept
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* kmap'd) includes the "process descriptor" which holds sequence data for
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* the doorbell, and one cacheline which actually *is* the doorbell; a
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* write to this will "ring the doorbell" (i.e. send an interrupt to the
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* GuC). The subsequent pages of the client object constitute the work
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* queue (a circular array of work items), again described in the process
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* descriptor. Work queue pages are mapped momentarily as required.
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*/
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struct intel_guc_client {
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struct i915_vma *vma;
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void *vaddr;
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struct i915_gem_context *owner;
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struct intel_guc *guc;
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/* bitmap of (host) engine ids */
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u32 engines;
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u32 priority;
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u32 stage_id;
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u32 proc_desc_offset;
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u16 doorbell_id;
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unsigned long doorbell_offset;
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/* Protects GuC client's WQ access */
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spinlock_t wq_lock;
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/* Per-engine counts of GuC submissions */
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u64 submissions[I915_NUM_ENGINES];
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/* For testing purposes, use nop WQ items instead of real ones */
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I915_SELFTEST_DECLARE(bool use_nop_wqi);
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};
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int intel_guc_submission_init(struct intel_guc *guc);
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int intel_guc_submission_enable(struct intel_guc *guc);
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void intel_guc_submission_disable(struct intel_guc *guc);
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void intel_guc_submission_fini(struct intel_guc *guc);
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int intel_guc_preempt_work_create(struct intel_guc *guc);
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void intel_guc_preempt_work_destroy(struct intel_guc *guc);
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#endif
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