582 lines
17 KiB
C
582 lines
17 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Eddie Dong <eddie.dong@intel.com>
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* Kevin Tian <kevin.tian@intel.com>
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*
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* Contributors:
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* Zhi Wang <zhi.a.wang@intel.com>
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* Changbin Du <changbin.du@intel.com>
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* Zhenyu Wang <zhenyuw@linux.intel.com>
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* Tina Zhang <tina.zhang@intel.com>
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* Bing Niu <bing.niu@intel.com>
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*
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*/
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#include "i915_drv.h"
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#include "gvt.h"
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#include "trace.h"
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#define GEN9_MOCS_SIZE 64
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/* Raw offset is appened to each line for convenience. */
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static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
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{RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
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{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
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{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
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{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
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{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
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{RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
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{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
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{RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
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{RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
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{RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
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{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
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{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
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{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
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{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
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{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
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{RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
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};
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static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
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{RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
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{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
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{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
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{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
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{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
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{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
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{RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
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{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
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{RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
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{RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
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{RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
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{RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
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{RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
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{RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
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{RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
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{RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
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{RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
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{RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
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{RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
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{RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
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{RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
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{RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
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{RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
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{RCS0, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
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{RCS0, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
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{RCS0, TRNULLDETCT, 0, false}, /* 0x4de8 */
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{RCS0, TRINVTILEDETCT, 0, false}, /* 0x4dec */
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{RCS0, TRVADR, 0, false}, /* 0x4df0 */
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{RCS0, TRTTE, 0, false}, /* 0x4df4 */
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{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
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{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
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{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
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{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
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{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
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{VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
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{VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
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{RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
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{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
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{RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
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{RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
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{RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
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{RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
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{RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
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{RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
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{RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
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{RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
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};
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static struct {
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bool initialized;
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u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];
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u32 l3cc_table[GEN9_MOCS_SIZE / 2];
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} gen9_render_mocs;
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static void load_render_mocs(struct drm_i915_private *dev_priv)
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{
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i915_reg_t offset;
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u32 regs[] = {
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[RCS0] = 0xc800,
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[VCS0] = 0xc900,
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[VCS1] = 0xca00,
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[BCS0] = 0xcc00,
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[VECS0] = 0xcb00,
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};
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int ring_id, i;
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for (ring_id = 0; ring_id < ARRAY_SIZE(regs); ring_id++) {
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if (!HAS_ENGINE(dev_priv, ring_id))
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continue;
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offset.reg = regs[ring_id];
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for (i = 0; i < GEN9_MOCS_SIZE; i++) {
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gen9_render_mocs.control_table[ring_id][i] =
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I915_READ_FW(offset);
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offset.reg += 4;
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}
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}
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offset.reg = 0xb020;
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for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
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gen9_render_mocs.l3cc_table[i] =
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I915_READ_FW(offset);
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offset.reg += 4;
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}
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gen9_render_mocs.initialized = true;
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}
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static int
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restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu,
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struct i915_request *req)
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{
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u32 *cs;
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int ret;
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struct engine_mmio *mmio;
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struct intel_gvt *gvt = vgpu->gvt;
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int ring_id = req->engine->id;
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int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id];
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if (count == 0)
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return 0;
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ret = req->engine->emit_flush(req, EMIT_BARRIER);
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if (ret)
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return ret;
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cs = intel_ring_begin(req, count * 2 + 2);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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*cs++ = MI_LOAD_REGISTER_IMM(count);
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for (mmio = gvt->engine_mmio_list.mmio;
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i915_mmio_reg_valid(mmio->reg); mmio++) {
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if (mmio->ring_id != ring_id ||
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!mmio->in_context)
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continue;
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*cs++ = i915_mmio_reg_offset(mmio->reg);
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*cs++ = vgpu_vreg_t(vgpu, mmio->reg) |
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(mmio->mask << 16);
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gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
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*(cs-2), *(cs-1), vgpu->id, ring_id);
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}
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*cs++ = MI_NOOP;
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intel_ring_advance(req, cs);
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ret = req->engine->emit_flush(req, EMIT_BARRIER);
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if (ret)
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return ret;
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return 0;
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}
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static int
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restore_render_mocs_control_for_inhibit(struct intel_vgpu *vgpu,
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struct i915_request *req)
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{
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unsigned int index;
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u32 *cs;
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cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE);
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for (index = 0; index < GEN9_MOCS_SIZE; index++) {
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*cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index));
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*cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index));
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gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
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*(cs-2), *(cs-1), vgpu->id, req->engine->id);
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}
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*cs++ = MI_NOOP;
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intel_ring_advance(req, cs);
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return 0;
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}
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static int
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restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu *vgpu,
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struct i915_request *req)
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{
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unsigned int index;
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u32 *cs;
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cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2);
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for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) {
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*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index));
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*cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index));
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gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
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*(cs-2), *(cs-1), vgpu->id, req->engine->id);
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}
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*cs++ = MI_NOOP;
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intel_ring_advance(req, cs);
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return 0;
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}
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/*
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* Use lri command to initialize the mmio which is in context state image for
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* inhibit context, it contains tracked engine mmio, render_mocs and
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* render_mocs_l3cc.
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*/
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int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
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struct i915_request *req)
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{
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int ret;
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u32 *cs;
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cs = intel_ring_begin(req, 2);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
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*cs++ = MI_NOOP;
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intel_ring_advance(req, cs);
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ret = restore_context_mmio_for_inhibit(vgpu, req);
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if (ret)
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goto out;
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/* no MOCS register in context except render engine */
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if (req->engine->id != RCS0)
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goto out;
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ret = restore_render_mocs_control_for_inhibit(vgpu, req);
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if (ret)
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goto out;
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ret = restore_render_mocs_l3cc_for_inhibit(vgpu, req);
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if (ret)
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goto out;
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out:
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cs = intel_ring_begin(req, 2);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
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*cs++ = MI_NOOP;
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intel_ring_advance(req, cs);
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return ret;
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}
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static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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struct intel_uncore *uncore = &dev_priv->uncore;
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struct intel_vgpu_submission *s = &vgpu->submission;
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enum forcewake_domains fw;
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i915_reg_t reg;
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u32 regs[] = {
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[RCS0] = 0x4260,
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[VCS0] = 0x4264,
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[VCS1] = 0x4268,
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[BCS0] = 0x426c,
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[VECS0] = 0x4270,
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};
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if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
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return;
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if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
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return;
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reg = _MMIO(regs[ring_id]);
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/* WaForceWakeRenderDuringMmioTLBInvalidate:skl
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* we need to put a forcewake when invalidating RCS TLB caches,
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* otherwise device can go to RC6 state and interrupt invalidation
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* process
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*/
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fw = intel_uncore_forcewake_for_reg(uncore, reg,
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FW_REG_READ | FW_REG_WRITE);
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if (ring_id == RCS0 && INTEL_GEN(dev_priv) >= 9)
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fw |= FORCEWAKE_RENDER;
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intel_uncore_forcewake_get(uncore, fw);
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intel_uncore_write_fw(uncore, reg, 0x1);
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if (wait_for_atomic((intel_uncore_read_fw(uncore, reg) == 0), 50))
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gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
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else
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vgpu_vreg_t(vgpu, reg) = 0;
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intel_uncore_forcewake_put(uncore, fw);
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gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
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}
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static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
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int ring_id)
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{
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struct drm_i915_private *dev_priv;
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i915_reg_t offset, l3_offset;
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u32 old_v, new_v;
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u32 regs[] = {
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[RCS0] = 0xc800,
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[VCS0] = 0xc900,
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[VCS1] = 0xca00,
|
|
[BCS0] = 0xcc00,
|
|
[VECS0] = 0xcb00,
|
|
};
|
|
int i;
|
|
|
|
dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
|
|
if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
|
|
return;
|
|
|
|
if (ring_id == RCS0 &&
|
|
(IS_KABYLAKE(dev_priv) ||
|
|
IS_BROXTON(dev_priv) ||
|
|
IS_COFFEELAKE(dev_priv)))
|
|
return;
|
|
|
|
if (!pre && !gen9_render_mocs.initialized)
|
|
load_render_mocs(dev_priv);
|
|
|
|
offset.reg = regs[ring_id];
|
|
for (i = 0; i < GEN9_MOCS_SIZE; i++) {
|
|
if (pre)
|
|
old_v = vgpu_vreg_t(pre, offset);
|
|
else
|
|
old_v = gen9_render_mocs.control_table[ring_id][i];
|
|
if (next)
|
|
new_v = vgpu_vreg_t(next, offset);
|
|
else
|
|
new_v = gen9_render_mocs.control_table[ring_id][i];
|
|
|
|
if (old_v != new_v)
|
|
I915_WRITE_FW(offset, new_v);
|
|
|
|
offset.reg += 4;
|
|
}
|
|
|
|
if (ring_id == RCS0) {
|
|
l3_offset.reg = 0xb020;
|
|
for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
|
|
if (pre)
|
|
old_v = vgpu_vreg_t(pre, l3_offset);
|
|
else
|
|
old_v = gen9_render_mocs.l3cc_table[i];
|
|
if (next)
|
|
new_v = vgpu_vreg_t(next, l3_offset);
|
|
else
|
|
new_v = gen9_render_mocs.l3cc_table[i];
|
|
|
|
if (old_v != new_v)
|
|
I915_WRITE_FW(l3_offset, new_v);
|
|
|
|
l3_offset.reg += 4;
|
|
}
|
|
}
|
|
}
|
|
|
|
#define CTX_CONTEXT_CONTROL_VAL 0x03
|
|
|
|
bool is_inhibit_context(struct intel_context *ce)
|
|
{
|
|
const u32 *reg_state = ce->lrc_reg_state;
|
|
u32 inhibit_mask =
|
|
_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
|
|
|
|
return inhibit_mask ==
|
|
(reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask);
|
|
}
|
|
|
|
/* Switch ring mmio values (context). */
|
|
static void switch_mmio(struct intel_vgpu *pre,
|
|
struct intel_vgpu *next,
|
|
int ring_id)
|
|
{
|
|
struct drm_i915_private *dev_priv;
|
|
struct intel_vgpu_submission *s;
|
|
struct engine_mmio *mmio;
|
|
u32 old_v, new_v;
|
|
|
|
dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
|
|
if (INTEL_GEN(dev_priv) >= 9)
|
|
switch_mocs(pre, next, ring_id);
|
|
|
|
for (mmio = dev_priv->gvt->engine_mmio_list.mmio;
|
|
i915_mmio_reg_valid(mmio->reg); mmio++) {
|
|
if (mmio->ring_id != ring_id)
|
|
continue;
|
|
/*
|
|
* No need to do save or restore of the mmio which is in context
|
|
* state image on kabylake, it's initialized by lri command and
|
|
* save or restore with context together.
|
|
*/
|
|
if ((IS_KABYLAKE(dev_priv) || IS_BROXTON(dev_priv)
|
|
|| IS_COFFEELAKE(dev_priv)) && mmio->in_context)
|
|
continue;
|
|
|
|
// save
|
|
if (pre) {
|
|
vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg);
|
|
if (mmio->mask)
|
|
vgpu_vreg_t(pre, mmio->reg) &=
|
|
~(mmio->mask << 16);
|
|
old_v = vgpu_vreg_t(pre, mmio->reg);
|
|
} else
|
|
old_v = mmio->value = I915_READ_FW(mmio->reg);
|
|
|
|
// restore
|
|
if (next) {
|
|
s = &next->submission;
|
|
/*
|
|
* No need to restore the mmio which is in context state
|
|
* image if it's not inhibit context, it will restore
|
|
* itself.
|
|
*/
|
|
if (mmio->in_context &&
|
|
!is_inhibit_context(s->shadow[ring_id]))
|
|
continue;
|
|
|
|
if (mmio->mask)
|
|
new_v = vgpu_vreg_t(next, mmio->reg) |
|
|
(mmio->mask << 16);
|
|
else
|
|
new_v = vgpu_vreg_t(next, mmio->reg);
|
|
} else {
|
|
if (mmio->in_context)
|
|
continue;
|
|
if (mmio->mask)
|
|
new_v = mmio->value | (mmio->mask << 16);
|
|
else
|
|
new_v = mmio->value;
|
|
}
|
|
|
|
I915_WRITE_FW(mmio->reg, new_v);
|
|
|
|
trace_render_mmio(pre ? pre->id : 0,
|
|
next ? next->id : 0,
|
|
"switch",
|
|
i915_mmio_reg_offset(mmio->reg),
|
|
old_v, new_v);
|
|
}
|
|
|
|
if (next)
|
|
handle_tlb_pending_event(next, ring_id);
|
|
}
|
|
|
|
/**
|
|
* intel_gvt_switch_render_mmio - switch mmio context of specific engine
|
|
* @pre: the last vGPU that own the engine
|
|
* @next: the vGPU to switch to
|
|
* @ring_id: specify the engine
|
|
*
|
|
* If pre is null indicates that host own the engine. If next is null
|
|
* indicates that we are switching to host workload.
|
|
*/
|
|
void intel_gvt_switch_mmio(struct intel_vgpu *pre,
|
|
struct intel_vgpu *next, int ring_id)
|
|
{
|
|
struct drm_i915_private *dev_priv;
|
|
|
|
if (WARN_ON(!pre && !next))
|
|
return;
|
|
|
|
gvt_dbg_render("switch ring %d from %s to %s\n", ring_id,
|
|
pre ? "vGPU" : "host", next ? "vGPU" : "HOST");
|
|
|
|
dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
|
|
|
|
/**
|
|
* We are using raw mmio access wrapper to improve the
|
|
* performace for batch mmio read/write, so we need
|
|
* handle forcewake mannually.
|
|
*/
|
|
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
|
switch_mmio(pre, next, ring_id);
|
|
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
|
}
|
|
|
|
/**
|
|
* intel_gvt_init_engine_mmio_context - Initiate the engine mmio list
|
|
* @gvt: GVT device
|
|
*
|
|
*/
|
|
void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
|
|
{
|
|
struct engine_mmio *mmio;
|
|
|
|
if (INTEL_GEN(gvt->dev_priv) >= 9)
|
|
gvt->engine_mmio_list.mmio = gen9_engine_mmio_list;
|
|
else
|
|
gvt->engine_mmio_list.mmio = gen8_engine_mmio_list;
|
|
|
|
for (mmio = gvt->engine_mmio_list.mmio;
|
|
i915_mmio_reg_valid(mmio->reg); mmio++) {
|
|
if (mmio->in_context) {
|
|
gvt->engine_mmio_list.ctx_mmio_count[mmio->ring_id]++;
|
|
intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg);
|
|
}
|
|
}
|
|
}
|