1767 lines
42 KiB
C
1767 lines
42 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* x86 SMP booting functions
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*
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* (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
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* (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
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* Copyright 2001 Andi Kleen, SuSE Labs.
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*
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* Much of the core SMP work is based on previous work by Thomas Radke, to
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* whom a great many thanks are extended.
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*
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* Thanks to Intel for making available several different Pentium,
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* Pentium Pro and Pentium-II/Xeon MP machines.
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* Original development of Linux SMP code supported by Caldera.
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*
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* Fixes
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* Felix Koop : NR_CPUS used properly
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* Jose Renau : Handle single CPU case.
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* Alan Cox : By repeated request 8) - Total BogoMIPS report.
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* Greg Wright : Fix for kernel stacks panic.
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* Erich Boleyn : MP v1.4 and additional changes.
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* Matthias Sattler : Changes for 2.1 kernel map.
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* Michel Lespinasse : Changes for 2.1 kernel map.
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* Michael Chastain : Change trampoline.S to gnu as.
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* Alan Cox : Dumb bug: 'B' step PPro's are fine
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* Ingo Molnar : Added APIC timers, based on code
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* from Jose Renau
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* Ingo Molnar : various cleanups and rewrites
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* Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
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* Maciej W. Rozycki : Bits for genuine 82489DX APICs
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* Andi Kleen : Changed for SMP boot into long mode.
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* Martin J. Bligh : Added support for multi-quad systems
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* Dave Jones : Report invalid combinations of Athlon CPUs.
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* Rusty Russell : Hacked into shape for new "hotplug" boot process.
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* Andi Kleen : Converted to new state machine.
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* Ashok Raj : CPU hotplug support
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* Glauber Costa : i386 and x86_64 integration
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/export.h>
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#include <linux/sched.h>
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#include <linux/sched/topology.h>
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#include <linux/sched/hotplug.h>
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#include <linux/sched/task_stack.h>
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#include <linux/percpu.h>
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#include <linux/memblock.h>
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#include <linux/err.h>
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#include <linux/nmi.h>
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#include <linux/tboot.h>
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#include <linux/stackprotector.h>
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#include <linux/gfp.h>
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#include <linux/cpuidle.h>
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#include <linux/numa.h>
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#include <asm/acpi.h>
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#include <asm/desc.h>
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#include <asm/nmi.h>
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#include <asm/irq.h>
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#include <asm/realmode.h>
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#include <asm/cpu.h>
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#include <asm/numa.h>
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#include <asm/pgtable.h>
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#include <asm/tlbflush.h>
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#include <asm/mtrr.h>
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#include <asm/mwait.h>
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#include <asm/apic.h>
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#include <asm/io_apic.h>
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#include <asm/fpu/internal.h>
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#include <asm/setup.h>
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#include <asm/uv/uv.h>
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#include <linux/mc146818rtc.h>
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#include <asm/i8259.h>
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#include <asm/misc.h>
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#include <asm/qspinlock.h>
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#include <asm/intel-family.h>
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#include <asm/cpu_device_id.h>
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#include <asm/spec-ctrl.h>
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#include <asm/hw_irq.h>
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/* representing HT siblings of each logical CPU */
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DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
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EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
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/* representing HT and core siblings of each logical CPU */
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DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
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EXPORT_PER_CPU_SYMBOL(cpu_core_map);
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/* representing HT, core, and die siblings of each logical CPU */
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DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
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EXPORT_PER_CPU_SYMBOL(cpu_die_map);
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DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
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/* Per CPU bogomips and other parameters */
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DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
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EXPORT_PER_CPU_SYMBOL(cpu_info);
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/* Logical package management. We might want to allocate that dynamically */
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unsigned int __max_logical_packages __read_mostly;
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EXPORT_SYMBOL(__max_logical_packages);
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static unsigned int logical_packages __read_mostly;
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static unsigned int logical_die __read_mostly;
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/* Maximum number of SMT threads on any online core */
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int __read_mostly __max_smt_threads = 1;
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/* Flag to indicate if a complete sched domain rebuild is required */
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bool x86_topology_update;
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int arch_update_cpu_topology(void)
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{
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int retval = x86_topology_update;
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x86_topology_update = false;
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return retval;
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}
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static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
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{
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unsigned long flags;
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spin_lock_irqsave(&rtc_lock, flags);
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CMOS_WRITE(0xa, 0xf);
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spin_unlock_irqrestore(&rtc_lock, flags);
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*((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
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start_eip >> 4;
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*((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
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start_eip & 0xf;
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}
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static inline void smpboot_restore_warm_reset_vector(void)
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{
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unsigned long flags;
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/*
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* Paranoid: Set warm reset code and vector here back
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* to default values.
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*/
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spin_lock_irqsave(&rtc_lock, flags);
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CMOS_WRITE(0, 0xf);
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spin_unlock_irqrestore(&rtc_lock, flags);
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*((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
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}
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/*
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* Report back to the Boot Processor during boot time or to the caller processor
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* during CPU online.
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*/
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static void smp_callin(void)
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{
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int cpuid;
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/*
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* If waken up by an INIT in an 82489DX configuration
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* cpu_callout_mask guarantees we don't get here before
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* an INIT_deassert IPI reaches our local APIC, so it is
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* now safe to touch our local APIC.
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*/
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cpuid = smp_processor_id();
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/*
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* the boot CPU has finished the init stage and is spinning
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* on callin_map until we finish. We are free to set up this
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* CPU, first the APIC. (this is probably redundant on most
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* boards)
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*/
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apic_ap_setup();
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/*
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* Save our processor parameters. Note: this information
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* is needed for clock calibration.
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*/
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smp_store_cpu_info(cpuid);
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/*
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* The topology information must be up to date before
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* calibrate_delay() and notify_cpu_starting().
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*/
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set_cpu_sibling_map(raw_smp_processor_id());
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/*
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* Get our bogomips.
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* Update loops_per_jiffy in cpu_data. Previous call to
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* smp_store_cpu_info() stored a value that is close but not as
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* accurate as the value just calculated.
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*/
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calibrate_delay();
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cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
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pr_debug("Stack at about %p\n", &cpuid);
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wmb();
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notify_cpu_starting(cpuid);
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/*
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* Allow the master to continue.
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*/
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cpumask_set_cpu(cpuid, cpu_callin_mask);
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}
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static int cpu0_logical_apicid;
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static int enable_start_cpu0;
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/*
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* Activate a secondary processor.
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*/
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static void notrace start_secondary(void *unused)
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{
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/*
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* Don't put *anything* except direct CPU state initialization
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* before cpu_init(), SMP booting is too fragile that we want to
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* limit the things done here to the most necessary things.
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*/
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cr4_init();
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#ifdef CONFIG_X86_32
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/* switch away from the initial page table */
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load_cr3(swapper_pg_dir);
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__flush_tlb_all();
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#endif
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load_current_idt();
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cpu_init();
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x86_cpuinit.early_percpu_clock_init();
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preempt_disable();
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smp_callin();
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enable_start_cpu0 = 0;
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/* otherwise gcc will move up smp_processor_id before the cpu_init */
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barrier();
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/*
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* Check TSC synchronization with the boot CPU:
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*/
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check_tsc_sync_target();
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speculative_store_bypass_ht_init();
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/*
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* Lock vector_lock, set CPU online and bring the vector
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* allocator online. Online must be set with vector_lock held
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* to prevent a concurrent irq setup/teardown from seeing a
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* half valid vector space.
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*/
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lock_vector_lock();
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set_cpu_online(smp_processor_id(), true);
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lapic_online();
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unlock_vector_lock();
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cpu_set_state_online(smp_processor_id());
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x86_platform.nmi_init();
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/* enable local interrupts */
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local_irq_enable();
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/* to prevent fake stack check failure in clock setup */
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boot_init_stack_canary();
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x86_cpuinit.setup_percpu_clockev();
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wmb();
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cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
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}
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/**
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* topology_is_primary_thread - Check whether CPU is the primary SMT thread
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* @cpu: CPU to check
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*/
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bool topology_is_primary_thread(unsigned int cpu)
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{
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return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
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}
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/**
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* topology_smt_supported - Check whether SMT is supported by the CPUs
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*/
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bool topology_smt_supported(void)
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{
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return smp_num_siblings > 1;
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}
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/**
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* topology_phys_to_logical_pkg - Map a physical package id to a logical
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*
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* Returns logical package id or -1 if not found
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*/
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int topology_phys_to_logical_pkg(unsigned int phys_pkg)
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{
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int cpu;
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for_each_possible_cpu(cpu) {
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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if (c->initialized && c->phys_proc_id == phys_pkg)
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return c->logical_proc_id;
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}
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return -1;
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}
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EXPORT_SYMBOL(topology_phys_to_logical_pkg);
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/**
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* topology_phys_to_logical_die - Map a physical die id to logical
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*
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* Returns logical die id or -1 if not found
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*/
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int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
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{
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int cpu;
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int proc_id = cpu_data(cur_cpu).phys_proc_id;
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for_each_possible_cpu(cpu) {
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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if (c->initialized && c->cpu_die_id == die_id &&
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c->phys_proc_id == proc_id)
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return c->logical_die_id;
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}
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return -1;
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}
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EXPORT_SYMBOL(topology_phys_to_logical_die);
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/**
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* topology_update_package_map - Update the physical to logical package map
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* @pkg: The physical package id as retrieved via CPUID
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* @cpu: The cpu for which this is updated
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*/
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int topology_update_package_map(unsigned int pkg, unsigned int cpu)
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{
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int new;
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/* Already available somewhere? */
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new = topology_phys_to_logical_pkg(pkg);
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if (new >= 0)
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goto found;
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new = logical_packages++;
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if (new != pkg) {
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pr_info("CPU %u Converting physical %u to logical package %u\n",
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cpu, pkg, new);
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}
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found:
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cpu_data(cpu).logical_proc_id = new;
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return 0;
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}
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/**
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* topology_update_die_map - Update the physical to logical die map
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* @die: The die id as retrieved via CPUID
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* @cpu: The cpu for which this is updated
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*/
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int topology_update_die_map(unsigned int die, unsigned int cpu)
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{
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int new;
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/* Already available somewhere? */
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new = topology_phys_to_logical_die(die, cpu);
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if (new >= 0)
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goto found;
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new = logical_die++;
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if (new != die) {
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pr_info("CPU %u Converting physical %u to logical die %u\n",
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cpu, die, new);
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}
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found:
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cpu_data(cpu).logical_die_id = new;
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return 0;
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}
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void __init smp_store_boot_cpu_info(void)
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{
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int id = 0; /* CPU 0 */
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struct cpuinfo_x86 *c = &cpu_data(id);
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*c = boot_cpu_data;
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c->cpu_index = id;
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topology_update_package_map(c->phys_proc_id, id);
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topology_update_die_map(c->cpu_die_id, id);
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c->initialized = true;
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}
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/*
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* The bootstrap kernel entry code has set these up. Save them for
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* a given CPU
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*/
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void smp_store_cpu_info(int id)
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{
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struct cpuinfo_x86 *c = &cpu_data(id);
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/* Copy boot_cpu_data only on the first bringup */
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if (!c->initialized)
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*c = boot_cpu_data;
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c->cpu_index = id;
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/*
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* During boot time, CPU0 has this setup already. Save the info when
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* bringing up AP or offlined CPU0.
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*/
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identify_secondary_cpu(c);
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c->initialized = true;
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}
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static bool
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topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
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{
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int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
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return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
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}
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static bool
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topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
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{
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int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
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return !WARN_ONCE(!topology_same_node(c, o),
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"sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
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"[node: %d != %d]. Ignoring dependency.\n",
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cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
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}
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#define link_mask(mfunc, c1, c2) \
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do { \
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cpumask_set_cpu((c1), mfunc(c2)); \
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cpumask_set_cpu((c2), mfunc(c1)); \
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} while (0)
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static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
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{
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if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
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int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
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if (c->phys_proc_id == o->phys_proc_id &&
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c->cpu_die_id == o->cpu_die_id &&
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per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
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if (c->cpu_core_id == o->cpu_core_id)
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return topology_sane(c, o, "smt");
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if ((c->cu_id != 0xff) &&
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(o->cu_id != 0xff) &&
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(c->cu_id == o->cu_id))
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return topology_sane(c, o, "smt");
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}
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} else if (c->phys_proc_id == o->phys_proc_id &&
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c->cpu_die_id == o->cpu_die_id &&
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c->cpu_core_id == o->cpu_core_id) {
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return topology_sane(c, o, "smt");
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}
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return false;
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}
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/*
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* Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
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*
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* These are Intel CPUs that enumerate an LLC that is shared by
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* multiple NUMA nodes. The LLC on these systems is shared for
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* off-package data access but private to the NUMA node (half
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* of the package) for on-package access.
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*
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* CPUID (the source of the information about the LLC) can only
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* enumerate the cache as being shared *or* unshared, but not
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* this particular configuration. The CPU in this case enumerates
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* the cache to be shared across the entire package (spanning both
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* NUMA nodes).
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*/
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static const struct x86_cpu_id snc_cpu[] = {
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X },
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{}
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};
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static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
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{
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int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
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/* Do not match if we do not have a valid APICID for cpu: */
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if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
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return false;
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/* Do not match if LLC id does not match: */
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if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
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return false;
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/*
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* Allow the SNC topology without warning. Return of false
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* means 'c' does not share the LLC of 'o'. This will be
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* reflected to userspace.
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*/
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if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
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return false;
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return topology_sane(c, o, "llc");
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}
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/*
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* Unlike the other levels, we do not enforce keeping a
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* multicore group inside a NUMA node. If this happens, we will
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* discard the MC level of the topology later.
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*/
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static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
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{
|
|
if (c->phys_proc_id == o->phys_proc_id)
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
|
|
{
|
|
if ((c->phys_proc_id == o->phys_proc_id) &&
|
|
(c->cpu_die_id == o->cpu_die_id))
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
|
|
#if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
|
|
static inline int x86_sched_itmt_flags(void)
|
|
{
|
|
return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
|
|
}
|
|
|
|
#ifdef CONFIG_SCHED_MC
|
|
static int x86_core_flags(void)
|
|
{
|
|
return cpu_core_flags() | x86_sched_itmt_flags();
|
|
}
|
|
#endif
|
|
#ifdef CONFIG_SCHED_SMT
|
|
static int x86_smt_flags(void)
|
|
{
|
|
return cpu_smt_flags() | x86_sched_itmt_flags();
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
|
|
#ifdef CONFIG_SCHED_SMT
|
|
{ cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
|
|
#endif
|
|
#ifdef CONFIG_SCHED_MC
|
|
{ cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
|
|
#endif
|
|
{ NULL, },
|
|
};
|
|
|
|
static struct sched_domain_topology_level x86_topology[] = {
|
|
#ifdef CONFIG_SCHED_SMT
|
|
{ cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
|
|
#endif
|
|
#ifdef CONFIG_SCHED_MC
|
|
{ cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
|
|
#endif
|
|
{ cpu_cpu_mask, SD_INIT_NAME(DIE) },
|
|
{ NULL, },
|
|
};
|
|
|
|
/*
|
|
* Set if a package/die has multiple NUMA nodes inside.
|
|
* AMD Magny-Cours, Intel Cluster-on-Die, and Intel
|
|
* Sub-NUMA Clustering have this.
|
|
*/
|
|
static bool x86_has_numa_in_package;
|
|
|
|
void set_cpu_sibling_map(int cpu)
|
|
{
|
|
bool has_smt = smp_num_siblings > 1;
|
|
bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
|
|
struct cpuinfo_x86 *c = &cpu_data(cpu);
|
|
struct cpuinfo_x86 *o;
|
|
int i, threads;
|
|
|
|
cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
|
|
|
|
if (!has_mp) {
|
|
cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
|
|
cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
|
|
cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
|
|
cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
|
|
c->booted_cores = 1;
|
|
return;
|
|
}
|
|
|
|
for_each_cpu(i, cpu_sibling_setup_mask) {
|
|
o = &cpu_data(i);
|
|
|
|
if ((i == cpu) || (has_smt && match_smt(c, o)))
|
|
link_mask(topology_sibling_cpumask, cpu, i);
|
|
|
|
if ((i == cpu) || (has_mp && match_llc(c, o)))
|
|
link_mask(cpu_llc_shared_mask, cpu, i);
|
|
|
|
}
|
|
|
|
/*
|
|
* This needs a separate iteration over the cpus because we rely on all
|
|
* topology_sibling_cpumask links to be set-up.
|
|
*/
|
|
for_each_cpu(i, cpu_sibling_setup_mask) {
|
|
o = &cpu_data(i);
|
|
|
|
if ((i == cpu) || (has_mp && match_pkg(c, o))) {
|
|
link_mask(topology_core_cpumask, cpu, i);
|
|
|
|
/*
|
|
* Does this new cpu bringup a new core?
|
|
*/
|
|
if (cpumask_weight(
|
|
topology_sibling_cpumask(cpu)) == 1) {
|
|
/*
|
|
* for each core in package, increment
|
|
* the booted_cores for this new cpu
|
|
*/
|
|
if (cpumask_first(
|
|
topology_sibling_cpumask(i)) == i)
|
|
c->booted_cores++;
|
|
/*
|
|
* increment the core count for all
|
|
* the other cpus in this package
|
|
*/
|
|
if (i != cpu)
|
|
cpu_data(i).booted_cores++;
|
|
} else if (i != cpu && !c->booted_cores)
|
|
c->booted_cores = cpu_data(i).booted_cores;
|
|
}
|
|
if (match_pkg(c, o) && !topology_same_node(c, o))
|
|
x86_has_numa_in_package = true;
|
|
|
|
if ((i == cpu) || (has_mp && match_die(c, o)))
|
|
link_mask(topology_die_cpumask, cpu, i);
|
|
}
|
|
|
|
threads = cpumask_weight(topology_sibling_cpumask(cpu));
|
|
if (threads > __max_smt_threads)
|
|
__max_smt_threads = threads;
|
|
}
|
|
|
|
/* maps the cpu to the sched domain representing multi-core */
|
|
const struct cpumask *cpu_coregroup_mask(int cpu)
|
|
{
|
|
return cpu_llc_shared_mask(cpu);
|
|
}
|
|
|
|
static void impress_friends(void)
|
|
{
|
|
int cpu;
|
|
unsigned long bogosum = 0;
|
|
/*
|
|
* Allow the user to impress friends.
|
|
*/
|
|
pr_debug("Before bogomips\n");
|
|
for_each_possible_cpu(cpu)
|
|
if (cpumask_test_cpu(cpu, cpu_callout_mask))
|
|
bogosum += cpu_data(cpu).loops_per_jiffy;
|
|
pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
|
|
num_online_cpus(),
|
|
bogosum/(500000/HZ),
|
|
(bogosum/(5000/HZ))%100);
|
|
|
|
pr_debug("Before bogocount - setting activated=1\n");
|
|
}
|
|
|
|
void __inquire_remote_apic(int apicid)
|
|
{
|
|
unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
|
|
const char * const names[] = { "ID", "VERSION", "SPIV" };
|
|
int timeout;
|
|
u32 status;
|
|
|
|
pr_info("Inquiring remote APIC 0x%x...\n", apicid);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(regs); i++) {
|
|
pr_info("... APIC 0x%x %s: ", apicid, names[i]);
|
|
|
|
/*
|
|
* Wait for idle.
|
|
*/
|
|
status = safe_apic_wait_icr_idle();
|
|
if (status)
|
|
pr_cont("a previous APIC delivery may have failed\n");
|
|
|
|
apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
|
|
|
|
timeout = 0;
|
|
do {
|
|
udelay(100);
|
|
status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
|
|
} while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
|
|
|
|
switch (status) {
|
|
case APIC_ICR_RR_VALID:
|
|
status = apic_read(APIC_RRR);
|
|
pr_cont("%08x\n", status);
|
|
break;
|
|
default:
|
|
pr_cont("failed\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* The Multiprocessor Specification 1.4 (1997) example code suggests
|
|
* that there should be a 10ms delay between the BSP asserting INIT
|
|
* and de-asserting INIT, when starting a remote processor.
|
|
* But that slows boot and resume on modern processors, which include
|
|
* many cores and don't require that delay.
|
|
*
|
|
* Cmdline "init_cpu_udelay=" is available to over-ride this delay.
|
|
* Modern processor families are quirked to remove the delay entirely.
|
|
*/
|
|
#define UDELAY_10MS_DEFAULT 10000
|
|
|
|
static unsigned int init_udelay = UINT_MAX;
|
|
|
|
static int __init cpu_init_udelay(char *str)
|
|
{
|
|
get_option(&str, &init_udelay);
|
|
|
|
return 0;
|
|
}
|
|
early_param("cpu_init_udelay", cpu_init_udelay);
|
|
|
|
static void __init smp_quirk_init_udelay(void)
|
|
{
|
|
/* if cmdline changed it from default, leave it alone */
|
|
if (init_udelay != UINT_MAX)
|
|
return;
|
|
|
|
/* if modern processor, use no delay */
|
|
if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
|
|
((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
|
|
((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
|
|
init_udelay = 0;
|
|
return;
|
|
}
|
|
/* else, use legacy delay */
|
|
init_udelay = UDELAY_10MS_DEFAULT;
|
|
}
|
|
|
|
/*
|
|
* Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
|
|
* INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
|
|
* won't ... remember to clear down the APIC, etc later.
|
|
*/
|
|
int
|
|
wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
|
|
{
|
|
unsigned long send_status, accept_status = 0;
|
|
int maxlvt;
|
|
|
|
/* Target chip */
|
|
/* Boot on the stack */
|
|
/* Kick the second */
|
|
apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
|
|
|
|
pr_debug("Waiting for send to finish...\n");
|
|
send_status = safe_apic_wait_icr_idle();
|
|
|
|
/*
|
|
* Give the other CPU some time to accept the IPI.
|
|
*/
|
|
udelay(200);
|
|
if (APIC_INTEGRATED(boot_cpu_apic_version)) {
|
|
maxlvt = lapic_get_maxlvt();
|
|
if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
|
|
apic_write(APIC_ESR, 0);
|
|
accept_status = (apic_read(APIC_ESR) & 0xEF);
|
|
}
|
|
pr_debug("NMI sent\n");
|
|
|
|
if (send_status)
|
|
pr_err("APIC never delivered???\n");
|
|
if (accept_status)
|
|
pr_err("APIC delivery error (%lx)\n", accept_status);
|
|
|
|
return (send_status | accept_status);
|
|
}
|
|
|
|
static int
|
|
wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
|
|
{
|
|
unsigned long send_status = 0, accept_status = 0;
|
|
int maxlvt, num_starts, j;
|
|
|
|
maxlvt = lapic_get_maxlvt();
|
|
|
|
/*
|
|
* Be paranoid about clearing APIC errors.
|
|
*/
|
|
if (APIC_INTEGRATED(boot_cpu_apic_version)) {
|
|
if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
|
|
apic_write(APIC_ESR, 0);
|
|
apic_read(APIC_ESR);
|
|
}
|
|
|
|
pr_debug("Asserting INIT\n");
|
|
|
|
/*
|
|
* Turn INIT on target chip
|
|
*/
|
|
/*
|
|
* Send IPI
|
|
*/
|
|
apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
|
|
phys_apicid);
|
|
|
|
pr_debug("Waiting for send to finish...\n");
|
|
send_status = safe_apic_wait_icr_idle();
|
|
|
|
udelay(init_udelay);
|
|
|
|
pr_debug("Deasserting INIT\n");
|
|
|
|
/* Target chip */
|
|
/* Send IPI */
|
|
apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
|
|
|
|
pr_debug("Waiting for send to finish...\n");
|
|
send_status = safe_apic_wait_icr_idle();
|
|
|
|
mb();
|
|
|
|
/*
|
|
* Should we send STARTUP IPIs ?
|
|
*
|
|
* Determine this based on the APIC version.
|
|
* If we don't have an integrated APIC, don't send the STARTUP IPIs.
|
|
*/
|
|
if (APIC_INTEGRATED(boot_cpu_apic_version))
|
|
num_starts = 2;
|
|
else
|
|
num_starts = 0;
|
|
|
|
/*
|
|
* Run STARTUP IPI loop.
|
|
*/
|
|
pr_debug("#startup loops: %d\n", num_starts);
|
|
|
|
for (j = 1; j <= num_starts; j++) {
|
|
pr_debug("Sending STARTUP #%d\n", j);
|
|
if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
|
|
apic_write(APIC_ESR, 0);
|
|
apic_read(APIC_ESR);
|
|
pr_debug("After apic_write\n");
|
|
|
|
/*
|
|
* STARTUP IPI
|
|
*/
|
|
|
|
/* Target chip */
|
|
/* Boot on the stack */
|
|
/* Kick the second */
|
|
apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
|
|
phys_apicid);
|
|
|
|
/*
|
|
* Give the other CPU some time to accept the IPI.
|
|
*/
|
|
if (init_udelay == 0)
|
|
udelay(10);
|
|
else
|
|
udelay(300);
|
|
|
|
pr_debug("Startup point 1\n");
|
|
|
|
pr_debug("Waiting for send to finish...\n");
|
|
send_status = safe_apic_wait_icr_idle();
|
|
|
|
/*
|
|
* Give the other CPU some time to accept the IPI.
|
|
*/
|
|
if (init_udelay == 0)
|
|
udelay(10);
|
|
else
|
|
udelay(200);
|
|
|
|
if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
|
|
apic_write(APIC_ESR, 0);
|
|
accept_status = (apic_read(APIC_ESR) & 0xEF);
|
|
if (send_status || accept_status)
|
|
break;
|
|
}
|
|
pr_debug("After Startup\n");
|
|
|
|
if (send_status)
|
|
pr_err("APIC never delivered???\n");
|
|
if (accept_status)
|
|
pr_err("APIC delivery error (%lx)\n", accept_status);
|
|
|
|
return (send_status | accept_status);
|
|
}
|
|
|
|
/* reduce the number of lines printed when booting a large cpu count system */
|
|
static void announce_cpu(int cpu, int apicid)
|
|
{
|
|
static int current_node = NUMA_NO_NODE;
|
|
int node = early_cpu_to_node(cpu);
|
|
static int width, node_width;
|
|
|
|
if (!width)
|
|
width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
|
|
|
|
if (!node_width)
|
|
node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
|
|
|
|
if (cpu == 1)
|
|
printk(KERN_INFO "x86: Booting SMP configuration:\n");
|
|
|
|
if (system_state < SYSTEM_RUNNING) {
|
|
if (node != current_node) {
|
|
if (current_node > (-1))
|
|
pr_cont("\n");
|
|
current_node = node;
|
|
|
|
printk(KERN_INFO ".... node %*s#%d, CPUs: ",
|
|
node_width - num_digits(node), " ", node);
|
|
}
|
|
|
|
/* Add padding for the BSP */
|
|
if (cpu == 1)
|
|
pr_cont("%*s", width + 1, " ");
|
|
|
|
pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
|
|
|
|
} else
|
|
pr_info("Booting Node %d Processor %d APIC 0x%x\n",
|
|
node, cpu, apicid);
|
|
}
|
|
|
|
static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
|
|
{
|
|
int cpu;
|
|
|
|
cpu = smp_processor_id();
|
|
if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
|
|
return NMI_HANDLED;
|
|
|
|
return NMI_DONE;
|
|
}
|
|
|
|
/*
|
|
* Wake up AP by INIT, INIT, STARTUP sequence.
|
|
*
|
|
* Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
|
|
* boot-strap code which is not a desired behavior for waking up BSP. To
|
|
* void the boot-strap code, wake up CPU0 by NMI instead.
|
|
*
|
|
* This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
|
|
* (i.e. physically hot removed and then hot added), NMI won't wake it up.
|
|
* We'll change this code in the future to wake up hard offlined CPU0 if
|
|
* real platform and request are available.
|
|
*/
|
|
static int
|
|
wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
|
|
int *cpu0_nmi_registered)
|
|
{
|
|
int id;
|
|
int boot_error;
|
|
|
|
preempt_disable();
|
|
|
|
/*
|
|
* Wake up AP by INIT, INIT, STARTUP sequence.
|
|
*/
|
|
if (cpu) {
|
|
boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Wake up BSP by nmi.
|
|
*
|
|
* Register a NMI handler to help wake up CPU0.
|
|
*/
|
|
boot_error = register_nmi_handler(NMI_LOCAL,
|
|
wakeup_cpu0_nmi, 0, "wake_cpu0");
|
|
|
|
if (!boot_error) {
|
|
enable_start_cpu0 = 1;
|
|
*cpu0_nmi_registered = 1;
|
|
if (apic->dest_logical == APIC_DEST_LOGICAL)
|
|
id = cpu0_logical_apicid;
|
|
else
|
|
id = apicid;
|
|
boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
|
|
}
|
|
|
|
out:
|
|
preempt_enable();
|
|
|
|
return boot_error;
|
|
}
|
|
|
|
int common_cpu_up(unsigned int cpu, struct task_struct *idle)
|
|
{
|
|
int ret;
|
|
|
|
/* Just in case we booted with a single CPU. */
|
|
alternatives_enable_smp();
|
|
|
|
per_cpu(current_task, cpu) = idle;
|
|
|
|
/* Initialize the interrupt stack(s) */
|
|
ret = irq_init_percpu_irqstack(cpu);
|
|
if (ret)
|
|
return ret;
|
|
|
|
#ifdef CONFIG_X86_32
|
|
/* Stack for startup_32 can be just as for start_secondary onwards */
|
|
per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
|
|
#else
|
|
initial_gs = per_cpu_offset(cpu);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
|
|
* (ie clustered apic addressing mode), this is a LOGICAL apic ID.
|
|
* Returns zero if CPU booted OK, else error code from
|
|
* ->wakeup_secondary_cpu.
|
|
*/
|
|
static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
|
|
int *cpu0_nmi_registered)
|
|
{
|
|
/* start_ip had better be page-aligned! */
|
|
unsigned long start_ip = real_mode_header->trampoline_start;
|
|
|
|
unsigned long boot_error = 0;
|
|
unsigned long timeout;
|
|
|
|
idle->thread.sp = (unsigned long)task_pt_regs(idle);
|
|
early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
|
|
initial_code = (unsigned long)start_secondary;
|
|
initial_stack = idle->thread.sp;
|
|
|
|
/* Enable the espfix hack for this CPU */
|
|
init_espfix_ap(cpu);
|
|
|
|
/* So we see what's up */
|
|
announce_cpu(cpu, apicid);
|
|
|
|
/*
|
|
* This grunge runs the startup process for
|
|
* the targeted processor.
|
|
*/
|
|
|
|
if (x86_platform.legacy.warm_reset) {
|
|
|
|
pr_debug("Setting warm reset code and vector.\n");
|
|
|
|
smpboot_setup_warm_reset_vector(start_ip);
|
|
/*
|
|
* Be paranoid about clearing APIC errors.
|
|
*/
|
|
if (APIC_INTEGRATED(boot_cpu_apic_version)) {
|
|
apic_write(APIC_ESR, 0);
|
|
apic_read(APIC_ESR);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* AP might wait on cpu_callout_mask in cpu_init() with
|
|
* cpu_initialized_mask set if previous attempt to online
|
|
* it timed-out. Clear cpu_initialized_mask so that after
|
|
* INIT/SIPI it could start with a clean state.
|
|
*/
|
|
cpumask_clear_cpu(cpu, cpu_initialized_mask);
|
|
smp_mb();
|
|
|
|
/*
|
|
* Wake up a CPU in difference cases:
|
|
* - Use the method in the APIC driver if it's defined
|
|
* Otherwise,
|
|
* - Use an INIT boot APIC message for APs or NMI for BSP.
|
|
*/
|
|
if (apic->wakeup_secondary_cpu)
|
|
boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
|
|
else
|
|
boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
|
|
cpu0_nmi_registered);
|
|
|
|
if (!boot_error) {
|
|
/*
|
|
* Wait 10s total for first sign of life from AP
|
|
*/
|
|
boot_error = -1;
|
|
timeout = jiffies + 10*HZ;
|
|
while (time_before(jiffies, timeout)) {
|
|
if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
|
|
/*
|
|
* Tell AP to proceed with initialization
|
|
*/
|
|
cpumask_set_cpu(cpu, cpu_callout_mask);
|
|
boot_error = 0;
|
|
break;
|
|
}
|
|
schedule();
|
|
}
|
|
}
|
|
|
|
if (!boot_error) {
|
|
/*
|
|
* Wait till AP completes initial initialization
|
|
*/
|
|
while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
|
|
/*
|
|
* Allow other tasks to run while we wait for the
|
|
* AP to come online. This also gives a chance
|
|
* for the MTRR work(triggered by the AP coming online)
|
|
* to be completed in the stop machine context.
|
|
*/
|
|
schedule();
|
|
}
|
|
}
|
|
|
|
if (x86_platform.legacy.warm_reset) {
|
|
/*
|
|
* Cleanup possible dangling ends...
|
|
*/
|
|
smpboot_restore_warm_reset_vector();
|
|
}
|
|
|
|
return boot_error;
|
|
}
|
|
|
|
int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
|
|
{
|
|
int apicid = apic->cpu_present_to_apicid(cpu);
|
|
int cpu0_nmi_registered = 0;
|
|
unsigned long flags;
|
|
int err, ret = 0;
|
|
|
|
lockdep_assert_irqs_enabled();
|
|
|
|
pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
|
|
|
|
if (apicid == BAD_APICID ||
|
|
!physid_isset(apicid, phys_cpu_present_map) ||
|
|
!apic->apic_id_valid(apicid)) {
|
|
pr_err("%s: bad cpu %d\n", __func__, cpu);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* Already booted CPU?
|
|
*/
|
|
if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
|
|
pr_debug("do_boot_cpu %d Already started\n", cpu);
|
|
return -ENOSYS;
|
|
}
|
|
|
|
/*
|
|
* Save current MTRR state in case it was changed since early boot
|
|
* (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
|
|
*/
|
|
mtrr_save_state();
|
|
|
|
/* x86 CPUs take themselves offline, so delayed offline is OK. */
|
|
err = cpu_check_up_prepare(cpu);
|
|
if (err && err != -EBUSY)
|
|
return err;
|
|
|
|
/* the FPU context is blank, nobody can own it */
|
|
per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
|
|
|
|
err = common_cpu_up(cpu, tidle);
|
|
if (err)
|
|
return err;
|
|
|
|
err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
|
|
if (err) {
|
|
pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
|
|
ret = -EIO;
|
|
goto unreg_nmi;
|
|
}
|
|
|
|
/*
|
|
* Check TSC synchronization with the AP (keep irqs disabled
|
|
* while doing so):
|
|
*/
|
|
local_irq_save(flags);
|
|
check_tsc_sync_source(cpu);
|
|
local_irq_restore(flags);
|
|
|
|
while (!cpu_online(cpu)) {
|
|
cpu_relax();
|
|
touch_nmi_watchdog();
|
|
}
|
|
|
|
unreg_nmi:
|
|
/*
|
|
* Clean up the nmi handler. Do this after the callin and callout sync
|
|
* to avoid impact of possible long unregister time.
|
|
*/
|
|
if (cpu0_nmi_registered)
|
|
unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* arch_disable_smp_support() - disables SMP support for x86 at runtime
|
|
*/
|
|
void arch_disable_smp_support(void)
|
|
{
|
|
disable_ioapic_support();
|
|
}
|
|
|
|
/*
|
|
* Fall back to non SMP mode after errors.
|
|
*
|
|
* RED-PEN audit/test this more. I bet there is more state messed up here.
|
|
*/
|
|
static __init void disable_smp(void)
|
|
{
|
|
pr_info("SMP disabled\n");
|
|
|
|
disable_ioapic_support();
|
|
|
|
init_cpu_present(cpumask_of(0));
|
|
init_cpu_possible(cpumask_of(0));
|
|
|
|
if (smp_found_config)
|
|
physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
|
|
else
|
|
physid_set_mask_of_physid(0, &phys_cpu_present_map);
|
|
cpumask_set_cpu(0, topology_sibling_cpumask(0));
|
|
cpumask_set_cpu(0, topology_core_cpumask(0));
|
|
cpumask_set_cpu(0, topology_die_cpumask(0));
|
|
}
|
|
|
|
/*
|
|
* Various sanity checks.
|
|
*/
|
|
static void __init smp_sanity_check(void)
|
|
{
|
|
preempt_disable();
|
|
|
|
#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
|
|
if (def_to_bigsmp && nr_cpu_ids > 8) {
|
|
unsigned int cpu;
|
|
unsigned nr;
|
|
|
|
pr_warn("More than 8 CPUs detected - skipping them\n"
|
|
"Use CONFIG_X86_BIGSMP\n");
|
|
|
|
nr = 0;
|
|
for_each_present_cpu(cpu) {
|
|
if (nr >= 8)
|
|
set_cpu_present(cpu, false);
|
|
nr++;
|
|
}
|
|
|
|
nr = 0;
|
|
for_each_possible_cpu(cpu) {
|
|
if (nr >= 8)
|
|
set_cpu_possible(cpu, false);
|
|
nr++;
|
|
}
|
|
|
|
nr_cpu_ids = 8;
|
|
}
|
|
#endif
|
|
|
|
if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
|
|
pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
|
|
hard_smp_processor_id());
|
|
|
|
physid_set(hard_smp_processor_id(), phys_cpu_present_map);
|
|
}
|
|
|
|
/*
|
|
* Should not be necessary because the MP table should list the boot
|
|
* CPU too, but we do it for the sake of robustness anyway.
|
|
*/
|
|
if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
|
|
pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
|
|
boot_cpu_physical_apicid);
|
|
physid_set(hard_smp_processor_id(), phys_cpu_present_map);
|
|
}
|
|
preempt_enable();
|
|
}
|
|
|
|
static void __init smp_cpu_index_default(void)
|
|
{
|
|
int i;
|
|
struct cpuinfo_x86 *c;
|
|
|
|
for_each_possible_cpu(i) {
|
|
c = &cpu_data(i);
|
|
/* mark all to hotplug */
|
|
c->cpu_index = nr_cpu_ids;
|
|
}
|
|
}
|
|
|
|
static void __init smp_get_logical_apicid(void)
|
|
{
|
|
if (x2apic_mode)
|
|
cpu0_logical_apicid = apic_read(APIC_LDR);
|
|
else
|
|
cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
|
|
}
|
|
|
|
/*
|
|
* Prepare for SMP bootup.
|
|
* @max_cpus: configured maximum number of CPUs, It is a legacy parameter
|
|
* for common interface support.
|
|
*/
|
|
void __init native_smp_prepare_cpus(unsigned int max_cpus)
|
|
{
|
|
unsigned int i;
|
|
|
|
smp_cpu_index_default();
|
|
|
|
/*
|
|
* Setup boot CPU information
|
|
*/
|
|
smp_store_boot_cpu_info(); /* Final full version of the data */
|
|
cpumask_copy(cpu_callin_mask, cpumask_of(0));
|
|
mb();
|
|
|
|
for_each_possible_cpu(i) {
|
|
zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
|
|
zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
|
|
zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
|
|
zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
|
|
}
|
|
|
|
/*
|
|
* Set 'default' x86 topology, this matches default_topology() in that
|
|
* it has NUMA nodes as a topology level. See also
|
|
* native_smp_cpus_done().
|
|
*
|
|
* Must be done before set_cpus_sibling_map() is ran.
|
|
*/
|
|
set_sched_topology(x86_topology);
|
|
|
|
set_cpu_sibling_map(0);
|
|
|
|
smp_sanity_check();
|
|
|
|
switch (apic_intr_mode) {
|
|
case APIC_PIC:
|
|
case APIC_VIRTUAL_WIRE_NO_CONFIG:
|
|
disable_smp();
|
|
return;
|
|
case APIC_SYMMETRIC_IO_NO_ROUTING:
|
|
disable_smp();
|
|
/* Setup local timer */
|
|
x86_init.timers.setup_percpu_clockev();
|
|
return;
|
|
case APIC_VIRTUAL_WIRE:
|
|
case APIC_SYMMETRIC_IO:
|
|
break;
|
|
}
|
|
|
|
/* Setup local timer */
|
|
x86_init.timers.setup_percpu_clockev();
|
|
|
|
smp_get_logical_apicid();
|
|
|
|
pr_info("CPU0: ");
|
|
print_cpu_info(&cpu_data(0));
|
|
|
|
uv_system_init();
|
|
|
|
set_mtrr_aps_delayed_init();
|
|
|
|
smp_quirk_init_udelay();
|
|
|
|
speculative_store_bypass_ht_init();
|
|
}
|
|
|
|
void arch_enable_nonboot_cpus_begin(void)
|
|
{
|
|
set_mtrr_aps_delayed_init();
|
|
}
|
|
|
|
void arch_enable_nonboot_cpus_end(void)
|
|
{
|
|
mtrr_aps_init();
|
|
}
|
|
|
|
/*
|
|
* Early setup to make printk work.
|
|
*/
|
|
void __init native_smp_prepare_boot_cpu(void)
|
|
{
|
|
int me = smp_processor_id();
|
|
switch_to_new_gdt(me);
|
|
/* already set me in cpu_online_mask in boot_cpu_init() */
|
|
cpumask_set_cpu(me, cpu_callout_mask);
|
|
cpu_set_state_online(me);
|
|
native_pv_lock_init();
|
|
}
|
|
|
|
void __init calculate_max_logical_packages(void)
|
|
{
|
|
int ncpus;
|
|
|
|
/*
|
|
* Today neither Intel nor AMD support heterogenous systems so
|
|
* extrapolate the boot cpu's data to all packages.
|
|
*/
|
|
ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
|
|
__max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
|
|
pr_info("Max logical packages: %u\n", __max_logical_packages);
|
|
}
|
|
|
|
void __init native_smp_cpus_done(unsigned int max_cpus)
|
|
{
|
|
pr_debug("Boot done\n");
|
|
|
|
calculate_max_logical_packages();
|
|
|
|
if (x86_has_numa_in_package)
|
|
set_sched_topology(x86_numa_in_package_topology);
|
|
|
|
nmi_selftest();
|
|
impress_friends();
|
|
mtrr_aps_init();
|
|
}
|
|
|
|
static int __initdata setup_possible_cpus = -1;
|
|
static int __init _setup_possible_cpus(char *str)
|
|
{
|
|
get_option(&str, &setup_possible_cpus);
|
|
return 0;
|
|
}
|
|
early_param("possible_cpus", _setup_possible_cpus);
|
|
|
|
|
|
/*
|
|
* cpu_possible_mask should be static, it cannot change as cpu's
|
|
* are onlined, or offlined. The reason is per-cpu data-structures
|
|
* are allocated by some modules at init time, and dont expect to
|
|
* do this dynamically on cpu arrival/departure.
|
|
* cpu_present_mask on the other hand can change dynamically.
|
|
* In case when cpu_hotplug is not compiled, then we resort to current
|
|
* behaviour, which is cpu_possible == cpu_present.
|
|
* - Ashok Raj
|
|
*
|
|
* Three ways to find out the number of additional hotplug CPUs:
|
|
* - If the BIOS specified disabled CPUs in ACPI/mptables use that.
|
|
* - The user can overwrite it with possible_cpus=NUM
|
|
* - Otherwise don't reserve additional CPUs.
|
|
* We do this because additional CPUs waste a lot of memory.
|
|
* -AK
|
|
*/
|
|
__init void prefill_possible_map(void)
|
|
{
|
|
int i, possible;
|
|
|
|
/* No boot processor was found in mptable or ACPI MADT */
|
|
if (!num_processors) {
|
|
if (boot_cpu_has(X86_FEATURE_APIC)) {
|
|
int apicid = boot_cpu_physical_apicid;
|
|
int cpu = hard_smp_processor_id();
|
|
|
|
pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
|
|
|
|
/* Make sure boot cpu is enumerated */
|
|
if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
|
|
apic->apic_id_valid(apicid))
|
|
generic_processor_info(apicid, boot_cpu_apic_version);
|
|
}
|
|
|
|
if (!num_processors)
|
|
num_processors = 1;
|
|
}
|
|
|
|
i = setup_max_cpus ?: 1;
|
|
if (setup_possible_cpus == -1) {
|
|
possible = num_processors;
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
if (setup_max_cpus)
|
|
possible += disabled_cpus;
|
|
#else
|
|
if (possible > i)
|
|
possible = i;
|
|
#endif
|
|
} else
|
|
possible = setup_possible_cpus;
|
|
|
|
total_cpus = max_t(int, possible, num_processors + disabled_cpus);
|
|
|
|
/* nr_cpu_ids could be reduced via nr_cpus= */
|
|
if (possible > nr_cpu_ids) {
|
|
pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
|
|
possible, nr_cpu_ids);
|
|
possible = nr_cpu_ids;
|
|
}
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
if (!setup_max_cpus)
|
|
#endif
|
|
if (possible > i) {
|
|
pr_warn("%d Processors exceeds max_cpus limit of %u\n",
|
|
possible, setup_max_cpus);
|
|
possible = i;
|
|
}
|
|
|
|
nr_cpu_ids = possible;
|
|
|
|
pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
|
|
possible, max_t(int, possible - num_processors, 0));
|
|
|
|
reset_cpu_possible_mask();
|
|
|
|
for (i = 0; i < possible; i++)
|
|
set_cpu_possible(i, true);
|
|
}
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
/* Recompute SMT state for all CPUs on offline */
|
|
static void recompute_smt_state(void)
|
|
{
|
|
int max_threads, cpu;
|
|
|
|
max_threads = 0;
|
|
for_each_online_cpu (cpu) {
|
|
int threads = cpumask_weight(topology_sibling_cpumask(cpu));
|
|
|
|
if (threads > max_threads)
|
|
max_threads = threads;
|
|
}
|
|
__max_smt_threads = max_threads;
|
|
}
|
|
|
|
static void remove_siblinginfo(int cpu)
|
|
{
|
|
int sibling;
|
|
struct cpuinfo_x86 *c = &cpu_data(cpu);
|
|
|
|
for_each_cpu(sibling, topology_core_cpumask(cpu)) {
|
|
cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
|
|
/*/
|
|
* last thread sibling in this cpu core going down
|
|
*/
|
|
if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
|
|
cpu_data(sibling).booted_cores--;
|
|
}
|
|
|
|
for_each_cpu(sibling, topology_die_cpumask(cpu))
|
|
cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
|
|
for_each_cpu(sibling, topology_sibling_cpumask(cpu))
|
|
cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
|
|
for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
|
|
cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
|
|
cpumask_clear(cpu_llc_shared_mask(cpu));
|
|
cpumask_clear(topology_sibling_cpumask(cpu));
|
|
cpumask_clear(topology_core_cpumask(cpu));
|
|
cpumask_clear(topology_die_cpumask(cpu));
|
|
c->cpu_core_id = 0;
|
|
c->booted_cores = 0;
|
|
cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
|
|
recompute_smt_state();
|
|
}
|
|
|
|
static void remove_cpu_from_maps(int cpu)
|
|
{
|
|
set_cpu_online(cpu, false);
|
|
cpumask_clear_cpu(cpu, cpu_callout_mask);
|
|
cpumask_clear_cpu(cpu, cpu_callin_mask);
|
|
/* was set by cpu_init() */
|
|
cpumask_clear_cpu(cpu, cpu_initialized_mask);
|
|
numa_remove_cpu(cpu);
|
|
}
|
|
|
|
void cpu_disable_common(void)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
|
|
remove_siblinginfo(cpu);
|
|
|
|
/* It's now safe to remove this processor from the online map */
|
|
lock_vector_lock();
|
|
remove_cpu_from_maps(cpu);
|
|
unlock_vector_lock();
|
|
fixup_irqs();
|
|
lapic_offline();
|
|
}
|
|
|
|
int native_cpu_disable(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = lapic_can_unplug_cpu();
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Disable the local APIC. Otherwise IPI broadcasts will reach
|
|
* it. It still responds normally to INIT, NMI, SMI, and SIPI
|
|
* messages.
|
|
*/
|
|
apic_soft_disable();
|
|
cpu_disable_common();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int common_cpu_die(unsigned int cpu)
|
|
{
|
|
int ret = 0;
|
|
|
|
/* We don't do anything here: idle task is faking death itself. */
|
|
|
|
/* They ack this in play_dead() by setting CPU_DEAD */
|
|
if (cpu_wait_death(cpu, 5)) {
|
|
if (system_state == SYSTEM_RUNNING)
|
|
pr_info("CPU %u is now offline\n", cpu);
|
|
} else {
|
|
pr_err("CPU %u didn't die...\n", cpu);
|
|
ret = -1;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
void native_cpu_die(unsigned int cpu)
|
|
{
|
|
common_cpu_die(cpu);
|
|
}
|
|
|
|
void play_dead_common(void)
|
|
{
|
|
idle_task_exit();
|
|
|
|
/* Ack it */
|
|
(void)cpu_report_death();
|
|
|
|
/*
|
|
* With physical CPU hotplug, we should halt the cpu
|
|
*/
|
|
local_irq_disable();
|
|
}
|
|
|
|
static bool wakeup_cpu0(void)
|
|
{
|
|
if (smp_processor_id() == 0 && enable_start_cpu0)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
/*
|
|
* We need to flush the caches before going to sleep, lest we have
|
|
* dirty data in our caches when we come back up.
|
|
*/
|
|
static inline void mwait_play_dead(void)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
unsigned int highest_cstate = 0;
|
|
unsigned int highest_subcstate = 0;
|
|
void *mwait_ptr;
|
|
int i;
|
|
|
|
if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
|
|
boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
|
|
return;
|
|
if (!this_cpu_has(X86_FEATURE_MWAIT))
|
|
return;
|
|
if (!this_cpu_has(X86_FEATURE_CLFLUSH))
|
|
return;
|
|
if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
|
|
return;
|
|
|
|
eax = CPUID_MWAIT_LEAF;
|
|
ecx = 0;
|
|
native_cpuid(&eax, &ebx, &ecx, &edx);
|
|
|
|
/*
|
|
* eax will be 0 if EDX enumeration is not valid.
|
|
* Initialized below to cstate, sub_cstate value when EDX is valid.
|
|
*/
|
|
if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
|
|
eax = 0;
|
|
} else {
|
|
edx >>= MWAIT_SUBSTATE_SIZE;
|
|
for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
|
|
if (edx & MWAIT_SUBSTATE_MASK) {
|
|
highest_cstate = i;
|
|
highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
|
|
}
|
|
}
|
|
eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
|
|
(highest_subcstate - 1);
|
|
}
|
|
|
|
/*
|
|
* This should be a memory location in a cache line which is
|
|
* unlikely to be touched by other processors. The actual
|
|
* content is immaterial as it is not actually modified in any way.
|
|
*/
|
|
mwait_ptr = ¤t_thread_info()->flags;
|
|
|
|
wbinvd();
|
|
|
|
while (1) {
|
|
/*
|
|
* The CLFLUSH is a workaround for erratum AAI65 for
|
|
* the Xeon 7400 series. It's not clear it is actually
|
|
* needed, but it should be harmless in either case.
|
|
* The WBINVD is insufficient due to the spurious-wakeup
|
|
* case where we return around the loop.
|
|
*/
|
|
mb();
|
|
clflush(mwait_ptr);
|
|
mb();
|
|
__monitor(mwait_ptr, 0, 0);
|
|
mb();
|
|
__mwait(eax, 0);
|
|
/*
|
|
* If NMI wants to wake up CPU0, start CPU0.
|
|
*/
|
|
if (wakeup_cpu0())
|
|
start_cpu0();
|
|
}
|
|
}
|
|
|
|
void hlt_play_dead(void)
|
|
{
|
|
if (__this_cpu_read(cpu_info.x86) >= 4)
|
|
wbinvd();
|
|
|
|
while (1) {
|
|
native_halt();
|
|
/*
|
|
* If NMI wants to wake up CPU0, start CPU0.
|
|
*/
|
|
if (wakeup_cpu0())
|
|
start_cpu0();
|
|
}
|
|
}
|
|
|
|
void native_play_dead(void)
|
|
{
|
|
play_dead_common();
|
|
tboot_shutdown(TB_SHUTDOWN_WFS);
|
|
|
|
mwait_play_dead(); /* Only returns on failure */
|
|
if (cpuidle_play_dead())
|
|
hlt_play_dead();
|
|
}
|
|
|
|
#else /* ... !CONFIG_HOTPLUG_CPU */
|
|
int native_cpu_disable(void)
|
|
{
|
|
return -ENOSYS;
|
|
}
|
|
|
|
void native_cpu_die(unsigned int cpu)
|
|
{
|
|
/* We said "no" in __cpu_disable */
|
|
BUG();
|
|
}
|
|
|
|
void native_play_dead(void)
|
|
{
|
|
BUG();
|
|
}
|
|
|
|
#endif
|