Jerome Brunet 093c3fac46 clk: meson: axg: add hifi pll clock ... Add the hifi pll to the axg clock controller. This clock maybe used as an input of the axg audio clock controller. It uses the same settings table as the gp0 pll but has a frac parameter allowing more precision. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>		2018-03-13 10:09:54 +01:00
..
Kconfig	clk: meson: use hhi syscon if available	2018-03-13 10:04:04 +01:00
Makefile	clk: meson: remove obsolete cpu_clk	2018-03-13 10:04:04 +01:00
axg.c	clk: meson: axg: add hifi pll clock	2018-03-13 10:09:54 +01:00
axg.h	clk: meson: axg: add hifi pll clock	2018-03-13 10:09:54 +01:00
clk-audio-divider.c	clk: meson: migrate the audio divider clock to clk_regmap	2018-03-13 10:04:02 +01:00
clk-mpll.c	clk: meson: split divider and gate part of mpll	2018-03-13 10:04:03 +01:00
clk-pll.c	clk: meson: add ROUND_CLOSEST to the pll driver	2018-03-13 10:09:49 +01:00
clk-regmap.c	clk: meson: add regmap clocks	2018-03-13 10:03:58 +01:00
clk-regmap.h	clk: meson: add regmap clocks	2018-03-13 10:03:58 +01:00
clkc.h	clk: meson: add ROUND_CLOSEST to the pll driver	2018-03-13 10:09:49 +01:00
gxbb-aoclk-32k.c	clk: meson: gxbb-aoclk: Add CEC 32k clock	2017-08-04 18:02:02 +02:00
gxbb-aoclk.c	clk: meson: switch gxbb ao_clk to clk_regmap	2018-03-13 10:03:59 +01:00
gxbb-aoclk.h	clk: meson: remove superseded aoclk_gate_regmap	2018-03-13 10:03:59 +01:00
gxbb.c	clk: meson: add gp0 frac parameter for axg and gxl	2018-03-13 10:09:47 +01:00
gxbb.h	clk: meson: split divider and gate part of mpll	2018-03-13 10:04:03 +01:00
meson8b.c	clk: meson: add fractional part of meson8b fixed_pll	2018-03-13 10:09:33 +01:00
meson8b.h	clk: meson: rework meson8b cpu clock	2018-03-13 10:04:03 +01:00