389 lines
10 KiB
C
389 lines
10 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/module.h>
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#include <drm/drm_drv.h>
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#include "amdgpu.h"
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bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
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{
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/* By now all MMIO pages except mailbox are blocked */
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/* if blocking is enabled in hypervisor. Choose the */
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/* SCRATCH_REG0 to test. */
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return RREG32_NO_KIQ(0xc040) == 0xffffffff;
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}
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void amdgpu_virt_init_setting(struct amdgpu_device *adev)
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{
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/* enable virtual display */
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if (adev->mode_info.num_crtc == 0)
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adev->mode_info.num_crtc = 1;
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adev->enable_virtual_display = true;
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adev->ddev->driver->driver_features &= ~DRIVER_ATOMIC;
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adev->cg_flags = 0;
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adev->pg_flags = 0;
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}
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void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
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uint32_t reg0, uint32_t reg1,
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uint32_t ref, uint32_t mask)
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{
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struct amdgpu_kiq *kiq = &adev->gfx.kiq;
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struct amdgpu_ring *ring = &kiq->ring;
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signed long r, cnt = 0;
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unsigned long flags;
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uint32_t seq;
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spin_lock_irqsave(&kiq->ring_lock, flags);
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amdgpu_ring_alloc(ring, 32);
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amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
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ref, mask);
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r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
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if (r)
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goto failed_undo;
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amdgpu_ring_commit(ring);
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spin_unlock_irqrestore(&kiq->ring_lock, flags);
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r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
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/* don't wait anymore for IRQ context */
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if (r < 1 && in_interrupt())
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goto failed_kiq;
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might_sleep();
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while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
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msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
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r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
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}
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if (cnt > MAX_KIQ_REG_TRY)
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goto failed_kiq;
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return;
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failed_undo:
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amdgpu_ring_undo(ring);
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spin_unlock_irqrestore(&kiq->ring_lock, flags);
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failed_kiq:
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pr_err("failed to write reg %x wait reg %x\n", reg0, reg1);
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}
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/**
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* amdgpu_virt_request_full_gpu() - request full gpu access
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* @amdgpu: amdgpu device.
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* @init: is driver init time.
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* When start to init/fini driver, first need to request full gpu access.
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* Return: Zero if request success, otherwise will return error.
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*/
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int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
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{
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struct amdgpu_virt *virt = &adev->virt;
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int r;
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if (virt->ops && virt->ops->req_full_gpu) {
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r = virt->ops->req_full_gpu(adev, init);
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if (r)
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return r;
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adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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return 0;
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}
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/**
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* amdgpu_virt_release_full_gpu() - release full gpu access
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* @amdgpu: amdgpu device.
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* @init: is driver init time.
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* When finishing driver init/fini, need to release full gpu access.
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* Return: Zero if release success, otherwise will returen error.
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*/
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int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
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{
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struct amdgpu_virt *virt = &adev->virt;
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int r;
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if (virt->ops && virt->ops->rel_full_gpu) {
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r = virt->ops->rel_full_gpu(adev, init);
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if (r)
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return r;
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adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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return 0;
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}
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/**
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* amdgpu_virt_reset_gpu() - reset gpu
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* @amdgpu: amdgpu device.
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* Send reset command to GPU hypervisor to reset GPU that VM is using
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* Return: Zero if reset success, otherwise will return error.
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*/
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int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
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{
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struct amdgpu_virt *virt = &adev->virt;
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int r;
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if (virt->ops && virt->ops->reset_gpu) {
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r = virt->ops->reset_gpu(adev);
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if (r)
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return r;
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adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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return 0;
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}
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void amdgpu_virt_request_init_data(struct amdgpu_device *adev)
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{
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struct amdgpu_virt *virt = &adev->virt;
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if (virt->ops && virt->ops->req_init_data)
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virt->ops->req_init_data(adev);
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if (adev->virt.req_init_data_ver > 0)
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DRM_INFO("host supports REQ_INIT_DATA handshake\n");
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else
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DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n");
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}
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/**
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* amdgpu_virt_wait_reset() - wait for reset gpu completed
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* @amdgpu: amdgpu device.
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* Wait for GPU reset completed.
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* Return: Zero if reset success, otherwise will return error.
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*/
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int amdgpu_virt_wait_reset(struct amdgpu_device *adev)
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{
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struct amdgpu_virt *virt = &adev->virt;
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if (!virt->ops || !virt->ops->wait_reset)
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return -EINVAL;
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return virt->ops->wait_reset(adev);
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}
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/**
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* amdgpu_virt_alloc_mm_table() - alloc memory for mm table
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* @amdgpu: amdgpu device.
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* MM table is used by UVD and VCE for its initialization
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* Return: Zero if allocate success.
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*/
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int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)
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{
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int r;
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if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)
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return 0;
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r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&adev->virt.mm_table.bo,
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&adev->virt.mm_table.gpu_addr,
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(void *)&adev->virt.mm_table.cpu_addr);
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if (r) {
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DRM_ERROR("failed to alloc mm table and error = %d.\n", r);
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return r;
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}
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memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);
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DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n",
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adev->virt.mm_table.gpu_addr,
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adev->virt.mm_table.cpu_addr);
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return 0;
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}
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/**
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* amdgpu_virt_free_mm_table() - free mm table memory
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* @amdgpu: amdgpu device.
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* Free MM table memory
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*/
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void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
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{
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if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)
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return;
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amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,
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&adev->virt.mm_table.gpu_addr,
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(void *)&adev->virt.mm_table.cpu_addr);
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adev->virt.mm_table.gpu_addr = 0;
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}
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int amdgpu_virt_fw_reserve_get_checksum(void *obj,
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unsigned long obj_size,
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unsigned int key,
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unsigned int chksum)
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{
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unsigned int ret = key;
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unsigned long i = 0;
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unsigned char *pos;
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pos = (char *)obj;
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/* calculate checksum */
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for (i = 0; i < obj_size; ++i)
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ret += *(pos + i);
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/* minus the chksum itself */
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pos = (char *)&chksum;
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for (i = 0; i < sizeof(chksum); ++i)
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ret -= *(pos + i);
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return ret;
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}
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void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
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{
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uint32_t pf2vf_size = 0;
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uint32_t checksum = 0;
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uint32_t checkval;
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char *str;
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adev->virt.fw_reserve.p_pf2vf = NULL;
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adev->virt.fw_reserve.p_vf2pf = NULL;
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if (adev->fw_vram_usage.va != NULL) {
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adev->virt.fw_reserve.p_pf2vf =
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(struct amd_sriov_msg_pf2vf_info_header *)(
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adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET);
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AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size);
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AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum);
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AMDGPU_FW_VRAM_PF2VF_READ(adev, feature_flags, &adev->virt.gim_feature);
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/* pf2vf message must be in 4K */
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if (pf2vf_size > 0 && pf2vf_size < 4096) {
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checkval = amdgpu_virt_fw_reserve_get_checksum(
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adev->virt.fw_reserve.p_pf2vf, pf2vf_size,
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adev->virt.fw_reserve.checksum_key, checksum);
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if (checkval == checksum) {
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adev->virt.fw_reserve.p_vf2pf =
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((void *)adev->virt.fw_reserve.p_pf2vf +
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pf2vf_size);
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memset((void *)adev->virt.fw_reserve.p_vf2pf, 0,
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sizeof(amdgim_vf2pf_info));
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AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.version,
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AMDGPU_FW_VRAM_VF2PF_VER);
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AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.size,
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sizeof(amdgim_vf2pf_info));
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AMDGPU_FW_VRAM_VF2PF_READ(adev, driver_version,
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&str);
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#ifdef MODULE
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if (THIS_MODULE->version != NULL)
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strcpy(str, THIS_MODULE->version);
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else
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#endif
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strcpy(str, "N/A");
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AMDGPU_FW_VRAM_VF2PF_WRITE(adev, driver_cert,
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0);
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AMDGPU_FW_VRAM_VF2PF_WRITE(adev, checksum,
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amdgpu_virt_fw_reserve_get_checksum(
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adev->virt.fw_reserve.p_vf2pf,
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pf2vf_size,
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adev->virt.fw_reserve.checksum_key, 0));
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}
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}
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}
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}
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void amdgpu_detect_virtualization(struct amdgpu_device *adev)
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{
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uint32_t reg;
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switch (adev->asic_type) {
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case CHIP_TONGA:
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case CHIP_FIJI:
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reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
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break;
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case CHIP_VEGA10:
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case CHIP_VEGA20:
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case CHIP_NAVI10:
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case CHIP_NAVI12:
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case CHIP_ARCTURUS:
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reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
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break;
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default: /* other chip doesn't support SRIOV */
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reg = 0;
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break;
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}
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if (reg & 1)
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adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
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if (reg & 0x80000000)
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adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
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if (!reg) {
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if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
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adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
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}
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}
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bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
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{
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return amdgpu_sriov_is_debug(adev) ? true : false;
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}
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bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
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{
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return amdgpu_sriov_is_normal(adev) ? true : false;
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}
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int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev)
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{
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if (!amdgpu_sriov_vf(adev) ||
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amdgpu_virt_access_debugfs_is_kiq(adev))
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return 0;
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if (amdgpu_virt_access_debugfs_is_mmio(adev))
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adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
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else
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return -EPERM;
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return 0;
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}
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void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev)
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{
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if (amdgpu_sriov_vf(adev))
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adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev)
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{
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enum amdgpu_sriov_vf_mode mode;
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if (amdgpu_sriov_vf(adev)) {
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if (amdgpu_sriov_is_pp_one_vf(adev))
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mode = SRIOV_VF_MODE_ONE_VF;
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else
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mode = SRIOV_VF_MODE_MULTI_VF;
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} else {
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mode = SRIOV_VF_MODE_BARE_METAL;
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}
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return mode;
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}
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