217 lines
5.7 KiB
C
217 lines
5.7 KiB
C
/*
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* Copyright (C) 2001,2002,2005 Broadcom Corporation
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/*
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* BCM1480/1455-specific HT support (looking like PCI)
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*
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* This module provides the glue between Linux's PCI subsystem
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* and the hardware. We basically provide glue for accessing
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* configuration space, and set up the translation for I/O
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* space accesses.
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*
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* To access configuration space, we use ioremap. In the 32-bit
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* kernel, this consumes either 4 or 8 page table pages, and 16MB of
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* kernel mapped memory. Hopefully neither of these should be a huge
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* problem.
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*
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/console.h>
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#include <linux/tty.h>
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#include <asm/sibyte/bcm1480_regs.h>
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#include <asm/sibyte/bcm1480_scd.h>
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#include <asm/sibyte/board.h>
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#include <asm/io.h>
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/*
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* Macros for calculating offsets into config space given a device
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* structure or dev/fun/reg
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*/
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#define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where))
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#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
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static void *ht_cfg_space;
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#define PCI_BUS_ENABLED 1
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#define PCI_DEVICE_MODE 2
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static int bcm1480ht_bus_status;
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#define PCI_BRIDGE_DEVICE 0
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#define HT_BRIDGE_DEVICE 1
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/*
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* HT's level-sensitive interrupts require EOI, which is generated
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* through a 4MB memory-mapped region
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*/
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unsigned long ht_eoi_space;
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/*
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* Read/write 32-bit values in config space.
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*/
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static inline u32 READCFG32(u32 addr)
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{
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return *(u32 *)(ht_cfg_space + (addr&~3));
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}
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static inline void WRITECFG32(u32 addr, u32 data)
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{
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*(u32 *)(ht_cfg_space + (addr & ~3)) = data;
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}
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/*
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* Some checks before doing config cycles:
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* In PCI Device Mode, hide everything on bus 0 except the LDT host
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* bridge. Otherwise, access is controlled by bridge MasterEn bits.
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*/
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static int bcm1480ht_can_access(struct pci_bus *bus, int devfn)
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{
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u32 devno;
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if (!(bcm1480ht_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
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return 0;
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if (bus->number == 0) {
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devno = PCI_SLOT(devfn);
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if (bcm1480ht_bus_status & PCI_DEVICE_MODE)
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return 0;
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}
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return 1;
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}
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/*
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* Read/write access functions for various sizes of values
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* in config space. Return all 1's for disallowed accesses
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* for a kludgy but adequate simulation of master aborts.
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*/
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static int bcm1480ht_pcibios_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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u32 data = 0;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (bcm1480ht_can_access(bus, devfn))
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data = READCFG32(CFGADDR(bus, devfn, where));
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else
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data = 0xFFFFFFFF;
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if (size == 2)
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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else
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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static int bcm1480ht_pcibios_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 cfgaddr = CFGADDR(bus, devfn, where);
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u32 data = 0;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (!bcm1480ht_can_access(bus, devfn))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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data = READCFG32(cfgaddr);
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if (size == 1)
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else if (size == 2)
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else
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data = val;
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WRITECFG32(cfgaddr, data);
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return PCIBIOS_SUCCESSFUL;
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}
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static int bcm1480ht_pcibios_get_busno(void)
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{
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return 0;
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}
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struct pci_ops bcm1480ht_pci_ops = {
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.read = bcm1480ht_pcibios_read,
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.write = bcm1480ht_pcibios_write,
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};
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static struct resource bcm1480ht_mem_resource = {
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.name = "BCM1480 HT MEM",
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.start = A_BCM1480_PHYS_HT_MEM_MATCH_BYTES,
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.end = A_BCM1480_PHYS_HT_MEM_MATCH_BYTES + 0x1fffffffUL,
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.flags = IORESOURCE_MEM,
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};
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static struct resource bcm1480ht_io_resource = {
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.name = "BCM1480 HT I/O",
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.start = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
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.end = A_BCM1480_PHYS_HT_IO_MATCH_BYTES + 0x01ffffffUL,
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.flags = IORESOURCE_IO,
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};
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struct pci_controller bcm1480ht_controller = {
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.pci_ops = &bcm1480ht_pci_ops,
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.mem_resource = &bcm1480ht_mem_resource,
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.io_resource = &bcm1480ht_io_resource,
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.index = 1,
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.get_busno = bcm1480ht_pcibios_get_busno,
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.io_offset = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
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};
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static int __init bcm1480ht_pcibios_init(void)
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{
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ht_cfg_space = ioremap(A_BCM1480_PHYS_HT_CFG_MATCH_BITS, 16*1024*1024);
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/* CFE doesn't always init all HT paths, so we always scan */
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bcm1480ht_bus_status |= PCI_BUS_ENABLED;
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ht_eoi_space = (unsigned long)
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ioremap(A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES,
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4 * 1024 * 1024);
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bcm1480ht_controller.io_map_base = (unsigned long)
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ioremap(A_BCM1480_PHYS_HT_IO_MATCH_BYTES, 65536);
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bcm1480ht_controller.io_map_base -= bcm1480ht_controller.io_offset;
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register_pci_controller(&bcm1480ht_controller);
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return 0;
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}
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arch_initcall(bcm1480ht_pcibios_init);
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