239 lines
6.6 KiB
C
239 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 Google LLC
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*/
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#include "ufshcd.h"
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#include "ufshcd-crypto.h"
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/* Blk-crypto modes supported by UFS crypto */
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static const struct ufs_crypto_alg_entry {
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enum ufs_crypto_alg ufs_alg;
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enum ufs_crypto_key_size ufs_key_size;
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} ufs_crypto_algs[BLK_ENCRYPTION_MODE_MAX] = {
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[BLK_ENCRYPTION_MODE_AES_256_XTS] = {
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.ufs_alg = UFS_CRYPTO_ALG_AES_XTS,
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.ufs_key_size = UFS_CRYPTO_KEY_SIZE_256,
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},
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};
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static int ufshcd_program_key(struct ufs_hba *hba,
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const union ufs_crypto_cfg_entry *cfg, int slot)
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{
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int i;
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u32 slot_offset = hba->crypto_cfg_register + slot * sizeof(*cfg);
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int err = 0;
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ufshcd_hold(hba, false);
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if (hba->vops && hba->vops->program_key) {
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err = hba->vops->program_key(hba, cfg, slot);
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goto out;
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}
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/* Ensure that CFGE is cleared before programming the key */
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ufshcd_writel(hba, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));
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for (i = 0; i < 16; i++) {
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ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[i]),
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slot_offset + i * sizeof(cfg->reg_val[0]));
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}
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/* Write dword 17 */
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ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[17]),
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slot_offset + 17 * sizeof(cfg->reg_val[0]));
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/* Dword 16 must be written last */
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ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[16]),
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slot_offset + 16 * sizeof(cfg->reg_val[0]));
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out:
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ufshcd_release(hba);
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return err;
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}
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static int ufshcd_crypto_keyslot_program(struct blk_keyslot_manager *ksm,
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const struct blk_crypto_key *key,
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unsigned int slot)
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{
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struct ufs_hba *hba = container_of(ksm, struct ufs_hba, ksm);
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const union ufs_crypto_cap_entry *ccap_array = hba->crypto_cap_array;
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const struct ufs_crypto_alg_entry *alg =
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&ufs_crypto_algs[key->crypto_cfg.crypto_mode];
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u8 data_unit_mask = key->crypto_cfg.data_unit_size / 512;
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int i;
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int cap_idx = -1;
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union ufs_crypto_cfg_entry cfg = {};
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int err;
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BUILD_BUG_ON(UFS_CRYPTO_KEY_SIZE_INVALID != 0);
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for (i = 0; i < hba->crypto_capabilities.num_crypto_cap; i++) {
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if (ccap_array[i].algorithm_id == alg->ufs_alg &&
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ccap_array[i].key_size == alg->ufs_key_size &&
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(ccap_array[i].sdus_mask & data_unit_mask)) {
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cap_idx = i;
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break;
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}
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}
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if (WARN_ON(cap_idx < 0))
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return -EOPNOTSUPP;
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cfg.data_unit_size = data_unit_mask;
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cfg.crypto_cap_idx = cap_idx;
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cfg.config_enable = UFS_CRYPTO_CONFIGURATION_ENABLE;
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if (ccap_array[cap_idx].algorithm_id == UFS_CRYPTO_ALG_AES_XTS) {
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/* In XTS mode, the blk_crypto_key's size is already doubled */
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memcpy(cfg.crypto_key, key->raw, key->size/2);
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memcpy(cfg.crypto_key + UFS_CRYPTO_KEY_MAX_SIZE/2,
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key->raw + key->size/2, key->size/2);
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} else {
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memcpy(cfg.crypto_key, key->raw, key->size);
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}
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err = ufshcd_program_key(hba, &cfg, slot);
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memzero_explicit(&cfg, sizeof(cfg));
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return err;
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}
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static int ufshcd_clear_keyslot(struct ufs_hba *hba, int slot)
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{
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/*
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* Clear the crypto cfg on the device. Clearing CFGE
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* might not be sufficient, so just clear the entire cfg.
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*/
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union ufs_crypto_cfg_entry cfg = {};
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return ufshcd_program_key(hba, &cfg, slot);
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}
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static int ufshcd_crypto_keyslot_evict(struct blk_keyslot_manager *ksm,
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const struct blk_crypto_key *key,
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unsigned int slot)
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{
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struct ufs_hba *hba = container_of(ksm, struct ufs_hba, ksm);
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return ufshcd_clear_keyslot(hba, slot);
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}
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bool ufshcd_crypto_enable(struct ufs_hba *hba)
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{
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if (!(hba->caps & UFSHCD_CAP_CRYPTO))
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return false;
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/* Reset might clear all keys, so reprogram all the keys. */
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blk_ksm_reprogram_all_keys(&hba->ksm);
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return true;
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}
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static const struct blk_ksm_ll_ops ufshcd_ksm_ops = {
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.keyslot_program = ufshcd_crypto_keyslot_program,
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.keyslot_evict = ufshcd_crypto_keyslot_evict,
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};
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static enum blk_crypto_mode_num
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ufshcd_find_blk_crypto_mode(union ufs_crypto_cap_entry cap)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ufs_crypto_algs); i++) {
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BUILD_BUG_ON(UFS_CRYPTO_KEY_SIZE_INVALID != 0);
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if (ufs_crypto_algs[i].ufs_alg == cap.algorithm_id &&
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ufs_crypto_algs[i].ufs_key_size == cap.key_size) {
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return i;
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}
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}
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return BLK_ENCRYPTION_MODE_INVALID;
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}
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/**
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* ufshcd_hba_init_crypto_capabilities - Read crypto capabilities, init crypto
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* fields in hba
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* @hba: Per adapter instance
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*
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* Return: 0 if crypto was initialized or is not supported, else a -errno value.
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*/
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int ufshcd_hba_init_crypto_capabilities(struct ufs_hba *hba)
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{
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int cap_idx;
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int err = 0;
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enum blk_crypto_mode_num blk_mode_num;
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/*
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* Don't use crypto if either the hardware doesn't advertise the
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* standard crypto capability bit *or* if the vendor specific driver
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* hasn't advertised that crypto is supported.
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*/
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if (!(hba->capabilities & MASK_CRYPTO_SUPPORT) ||
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!(hba->caps & UFSHCD_CAP_CRYPTO))
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goto out;
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hba->crypto_capabilities.reg_val =
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cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP));
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hba->crypto_cfg_register =
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(u32)hba->crypto_capabilities.config_array_ptr * 0x100;
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hba->crypto_cap_array =
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devm_kcalloc(hba->dev, hba->crypto_capabilities.num_crypto_cap,
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sizeof(hba->crypto_cap_array[0]), GFP_KERNEL);
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if (!hba->crypto_cap_array) {
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err = -ENOMEM;
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goto out;
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}
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/* The actual number of configurations supported is (CFGC+1) */
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err = devm_blk_ksm_init(hba->dev, &hba->ksm,
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hba->crypto_capabilities.config_count + 1);
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if (err)
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goto out;
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hba->ksm.ksm_ll_ops = ufshcd_ksm_ops;
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/* UFS only supports 8 bytes for any DUN */
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hba->ksm.max_dun_bytes_supported = 8;
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hba->ksm.dev = hba->dev;
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/*
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* Cache all the UFS crypto capabilities and advertise the supported
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* crypto modes and data unit sizes to the block layer.
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*/
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for (cap_idx = 0; cap_idx < hba->crypto_capabilities.num_crypto_cap;
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cap_idx++) {
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hba->crypto_cap_array[cap_idx].reg_val =
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cpu_to_le32(ufshcd_readl(hba,
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REG_UFS_CRYPTOCAP +
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cap_idx * sizeof(__le32)));
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blk_mode_num = ufshcd_find_blk_crypto_mode(
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hba->crypto_cap_array[cap_idx]);
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if (blk_mode_num != BLK_ENCRYPTION_MODE_INVALID)
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hba->ksm.crypto_modes_supported[blk_mode_num] |=
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hba->crypto_cap_array[cap_idx].sdus_mask * 512;
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}
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return 0;
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out:
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/* Indicate that init failed by clearing UFSHCD_CAP_CRYPTO */
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hba->caps &= ~UFSHCD_CAP_CRYPTO;
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return err;
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}
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/**
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* ufshcd_init_crypto - Initialize crypto hardware
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* @hba: Per adapter instance
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*/
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void ufshcd_init_crypto(struct ufs_hba *hba)
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{
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int slot;
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if (!(hba->caps & UFSHCD_CAP_CRYPTO))
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return;
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/* Clear all keyslots - the number of keyslots is (CFGC + 1) */
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for (slot = 0; slot < hba->crypto_capabilities.config_count + 1; slot++)
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ufshcd_clear_keyslot(hba, slot);
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}
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void ufshcd_crypto_setup_rq_keyslot_manager(struct ufs_hba *hba,
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struct request_queue *q)
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{
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if (hba->caps & UFSHCD_CAP_CRYPTO)
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blk_ksm_register(&hba->ksm, q);
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}
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