483 lines
12 KiB
C
483 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2015 - 2016 Cavium, Inc.
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*/
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#include <linux/bitfield.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/pci-acpi.h>
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#include <linux/pci-ecam.h>
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#include <linux/platform_device.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include "../pci.h"
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#if defined(CONFIG_PCI_HOST_THUNDER_PEM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
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#define PEM_CFG_WR 0x28
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#define PEM_CFG_RD 0x30
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/*
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* Enhanced Configuration Access Mechanism (ECAM)
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*
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* N.B. This is a non-standard platform-specific ECAM bus shift value. For
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* standard values defined in the PCI Express Base Specification see
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* include/linux/pci-ecam.h.
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*/
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#define THUNDER_PCIE_ECAM_BUS_SHIFT 24
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struct thunder_pem_pci {
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u32 ea_entry[3];
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void __iomem *pem_reg_base;
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};
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static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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u64 read_val, tmp_val;
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struct pci_config_window *cfg = bus->sysdata;
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struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
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if (devfn != 0 || where >= 2048) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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/*
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* 32-bit accesses only. Write the address to the low order
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* bits of PEM_CFG_RD, then trigger the read by reading back.
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* The config data lands in the upper 32-bits of PEM_CFG_RD.
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*/
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read_val = where & ~3ull;
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writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);
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read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
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read_val >>= 32;
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/*
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* The config space contains some garbage, fix it up. Also
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* synthesize an EA capability for the BAR used by MSI-X.
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*/
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switch (where & ~3) {
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case 0x40:
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read_val &= 0xffff00ff;
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read_val |= 0x00007000; /* Skip MSI CAP */
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break;
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case 0x70: /* Express Cap */
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/*
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* Change PME interrupt to vector 2 on T88 where it
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* reads as 0, else leave it alone.
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*/
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if (!(read_val & (0x1f << 25)))
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read_val |= (2u << 25);
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break;
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case 0xb0: /* MSI-X Cap */
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/* TableSize=2 or 4, Next Cap is EA */
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read_val &= 0xc00000ff;
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/*
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* If Express Cap(0x70) raw PME vector reads as 0 we are on
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* T88 and TableSize is reported as 4, else TableSize
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* is 2.
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*/
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writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD);
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tmp_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
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tmp_val >>= 32;
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if (!(tmp_val & (0x1f << 25)))
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read_val |= 0x0003bc00;
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else
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read_val |= 0x0001bc00;
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break;
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case 0xb4:
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/* Table offset=0, BIR=0 */
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read_val = 0x00000000;
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break;
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case 0xb8:
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/* BPA offset=0xf0000, BIR=0 */
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read_val = 0x000f0000;
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break;
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case 0xbc:
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/* EA, 1 entry, no next Cap */
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read_val = 0x00010014;
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break;
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case 0xc0:
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/* DW2 for type-1 */
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read_val = 0x00000000;
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break;
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case 0xc4:
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/* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */
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read_val = 0x80ff0003;
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break;
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case 0xc8:
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read_val = pem_pci->ea_entry[0];
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break;
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case 0xcc:
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read_val = pem_pci->ea_entry[1];
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break;
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case 0xd0:
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read_val = pem_pci->ea_entry[2];
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break;
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default:
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break;
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}
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read_val >>= (8 * (where & 3));
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switch (size) {
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case 1:
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read_val &= 0xff;
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break;
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case 2:
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read_val &= 0xffff;
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break;
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default:
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break;
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}
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*val = read_val;
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return PCIBIOS_SUCCESSFUL;
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}
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static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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struct pci_config_window *cfg = bus->sysdata;
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if (bus->number < cfg->busr.start ||
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bus->number > cfg->busr.end)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* The first device on the bus is the PEM PCIe bridge.
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* Special case its config access.
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*/
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if (bus->number == cfg->busr.start)
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return thunder_pem_bridge_read(bus, devfn, where, size, val);
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return pci_generic_config_read(bus, devfn, where, size, val);
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}
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/*
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* Some of the w1c_bits below also include read-only or non-writable
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* reserved bits, this makes the code simpler and is OK as the bits
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* are not affected by writing zeros to them.
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*/
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static u32 thunder_pem_bridge_w1c_bits(u64 where_aligned)
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{
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u32 w1c_bits = 0;
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switch (where_aligned) {
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case 0x04: /* Command/Status */
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case 0x1c: /* Base and I/O Limit/Secondary Status */
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w1c_bits = 0xff000000;
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break;
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case 0x44: /* Power Management Control and Status */
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w1c_bits = 0xfffffe00;
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break;
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case 0x78: /* Device Control/Device Status */
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case 0x80: /* Link Control/Link Status */
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case 0x88: /* Slot Control/Slot Status */
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case 0x90: /* Root Status */
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case 0xa0: /* Link Control 2 Registers/Link Status 2 */
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w1c_bits = 0xffff0000;
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break;
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case 0x104: /* Uncorrectable Error Status */
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case 0x110: /* Correctable Error Status */
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case 0x130: /* Error Status */
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case 0x160: /* Link Control 4 */
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w1c_bits = 0xffffffff;
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break;
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default:
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break;
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}
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return w1c_bits;
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}
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/* Some bits must be written to one so they appear to be read-only. */
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static u32 thunder_pem_bridge_w1_bits(u64 where_aligned)
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{
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u32 w1_bits;
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switch (where_aligned) {
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case 0x1c: /* I/O Base / I/O Limit, Secondary Status */
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/* Force 32-bit I/O addressing. */
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w1_bits = 0x0101;
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break;
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case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */
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/* Force 64-bit addressing */
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w1_bits = 0x00010001;
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break;
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default:
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w1_bits = 0;
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break;
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}
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return w1_bits;
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}
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static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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struct pci_config_window *cfg = bus->sysdata;
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struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
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u64 write_val, read_val;
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u64 where_aligned = where & ~3ull;
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u32 mask = 0;
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if (devfn != 0 || where >= 2048)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* 32-bit accesses only. If the write is for a size smaller
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* than 32-bits, we must first read the 32-bit value and merge
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* in the desired bits and then write the whole 32-bits back
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* out.
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*/
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switch (size) {
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case 1:
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writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
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read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
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read_val >>= 32;
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mask = ~(0xff << (8 * (where & 3)));
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read_val &= mask;
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val = (val & 0xff) << (8 * (where & 3));
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val |= (u32)read_val;
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break;
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case 2:
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writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
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read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
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read_val >>= 32;
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mask = ~(0xffff << (8 * (where & 3)));
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read_val &= mask;
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val = (val & 0xffff) << (8 * (where & 3));
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val |= (u32)read_val;
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break;
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default:
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break;
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}
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/*
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* By expanding the write width to 32 bits, we may
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* inadvertently hit some W1C bits that were not intended to
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* be written. Calculate the mask that must be applied to the
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* data to be written to avoid these cases.
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*/
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if (mask) {
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u32 w1c_bits = thunder_pem_bridge_w1c_bits(where);
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if (w1c_bits) {
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mask &= w1c_bits;
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val &= ~mask;
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}
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}
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/*
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* Some bits must be read-only with value of one. Since the
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* access method allows these to be cleared if a zero is
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* written, force them to one before writing.
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*/
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val |= thunder_pem_bridge_w1_bits(where_aligned);
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/*
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* Low order bits are the config address, the high order 32
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* bits are the data to be written.
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*/
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write_val = (((u64)val) << 32) | where_aligned;
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writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR);
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return PCIBIOS_SUCCESSFUL;
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}
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static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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struct pci_config_window *cfg = bus->sysdata;
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if (bus->number < cfg->busr.start ||
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bus->number > cfg->busr.end)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* The first device on the bus is the PEM PCIe bridge.
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* Special case its config access.
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*/
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if (bus->number == cfg->busr.start)
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return thunder_pem_bridge_write(bus, devfn, where, size, val);
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return pci_generic_config_write(bus, devfn, where, size, val);
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}
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static int thunder_pem_init(struct device *dev, struct pci_config_window *cfg,
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struct resource *res_pem)
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{
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struct thunder_pem_pci *pem_pci;
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resource_size_t bar4_start;
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pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL);
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if (!pem_pci)
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return -ENOMEM;
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pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000);
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if (!pem_pci->pem_reg_base)
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return -ENOMEM;
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/*
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* The MSI-X BAR for the PEM and AER interrupts is located at
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* a fixed offset from the PEM register base. Generate a
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* fragment of the synthesized Enhanced Allocation capability
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* structure here for the BAR.
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*/
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bar4_start = res_pem->start + 0xf00000;
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pem_pci->ea_entry[0] = lower_32_bits(bar4_start) | 2;
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pem_pci->ea_entry[1] = lower_32_bits(res_pem->end - bar4_start) & ~3u;
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pem_pci->ea_entry[2] = upper_32_bits(bar4_start);
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cfg->priv = pem_pci;
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return 0;
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}
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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#define PEM_RES_BASE 0x87e0c0000000ULL
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#define PEM_NODE_MASK GENMASK_ULL(45, 44)
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#define PEM_INDX_MASK GENMASK_ULL(26, 24)
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#define PEM_MIN_DOM_IN_NODE 4
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#define PEM_MAX_DOM_IN_NODE 10
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static void thunder_pem_reserve_range(struct device *dev, int seg,
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struct resource *r)
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{
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resource_size_t start = r->start, end = r->end;
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struct resource *res;
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const char *regionid;
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regionid = kasprintf(GFP_KERNEL, "PEM RC:%d", seg);
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if (!regionid)
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return;
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res = request_mem_region(start, end - start + 1, regionid);
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if (res)
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res->flags &= ~IORESOURCE_BUSY;
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else
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kfree(regionid);
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dev_info(dev, "%pR %s reserved\n", r,
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res ? "has been" : "could not be");
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}
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static void thunder_pem_legacy_fw(struct acpi_pci_root *root,
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struct resource *res_pem)
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{
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int node = acpi_get_node(root->device->handle);
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int index;
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if (node == NUMA_NO_NODE)
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node = 0;
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index = root->segment - PEM_MIN_DOM_IN_NODE;
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index -= node * PEM_MAX_DOM_IN_NODE;
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res_pem->start = PEM_RES_BASE | FIELD_PREP(PEM_NODE_MASK, node) |
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FIELD_PREP(PEM_INDX_MASK, index);
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res_pem->flags = IORESOURCE_MEM;
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}
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static int thunder_pem_acpi_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct acpi_device *adev = to_acpi_device(dev);
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struct acpi_pci_root *root = acpi_driver_data(adev);
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struct resource *res_pem;
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int ret;
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res_pem = devm_kzalloc(&adev->dev, sizeof(*res_pem), GFP_KERNEL);
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if (!res_pem)
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return -ENOMEM;
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ret = acpi_get_rc_resources(dev, "CAVA02B", root->segment, res_pem);
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/*
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* If we fail to gather resources it means that we run with old
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* FW where we need to calculate PEM-specific resources manually.
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*/
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if (ret) {
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thunder_pem_legacy_fw(root, res_pem);
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/*
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* Reserve 64K size PEM specific resources. The full 16M range
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* size is required for thunder_pem_init() call.
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*/
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res_pem->end = res_pem->start + SZ_64K - 1;
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thunder_pem_reserve_range(dev, root->segment, res_pem);
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res_pem->end = res_pem->start + SZ_16M - 1;
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/* Reserve PCI configuration space as well. */
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thunder_pem_reserve_range(dev, root->segment, &cfg->res);
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}
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return thunder_pem_init(dev, cfg, res_pem);
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}
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const struct pci_ecam_ops thunder_pem_ecam_ops = {
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.bus_shift = THUNDER_PCIE_ECAM_BUS_SHIFT,
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.init = thunder_pem_acpi_init,
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.pci_ops = {
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.map_bus = pci_ecam_map_bus,
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.read = thunder_pem_config_read,
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.write = thunder_pem_config_write,
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}
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};
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#endif
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#ifdef CONFIG_PCI_HOST_THUNDER_PEM
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static int thunder_pem_platform_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *res_pem;
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if (!dev->of_node)
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return -EINVAL;
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/*
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* The second register range is the PEM bridge to the PCIe
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* bus. It has a different config access method than those
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* devices behind the bridge.
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*/
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res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res_pem) {
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dev_err(dev, "missing \"reg[1]\"property\n");
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return -EINVAL;
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}
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return thunder_pem_init(dev, cfg, res_pem);
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}
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static const struct pci_ecam_ops pci_thunder_pem_ops = {
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.bus_shift = THUNDER_PCIE_ECAM_BUS_SHIFT,
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.init = thunder_pem_platform_init,
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.pci_ops = {
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.map_bus = pci_ecam_map_bus,
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.read = thunder_pem_config_read,
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.write = thunder_pem_config_write,
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}
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};
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static const struct of_device_id thunder_pem_of_match[] = {
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{
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.compatible = "cavium,pci-host-thunder-pem",
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.data = &pci_thunder_pem_ops,
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},
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{ },
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};
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static struct platform_driver thunder_pem_driver = {
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = thunder_pem_of_match,
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.suppress_bind_attrs = true,
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},
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.probe = pci_host_common_probe,
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};
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builtin_platform_driver(thunder_pem_driver);
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#endif
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#endif
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