128 lines
3.3 KiB
C
128 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/G2L CPG driver
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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#include "renesas-rzg2l-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A07G044_OSCCLK,
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/* External Input Clocks */
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CLK_EXTAL,
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/* Internal Core Clocks */
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CLK_OSC_DIV1000,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL2_DIV2,
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CLK_PLL2_DIV16,
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CLK_PLL2_DIV20,
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CLK_PLL3,
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CLK_PLL3_DIV2,
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CLK_PLL3_DIV4,
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CLK_PLL3_DIV8,
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CLK_PLL4,
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CLK_PLL5,
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CLK_PLL5_DIV2,
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CLK_PLL6,
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/* Module Clocks */
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MOD_CLK_BASE,
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};
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/* Divider tables */
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static const struct clk_div_table dtable_3b[] = {
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{0, 1},
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{1, 2},
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{2, 4},
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{3, 8},
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{4, 32},
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};
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static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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/* Internal Core Clocks */
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DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
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DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
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DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
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DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
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DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),
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DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
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DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),
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DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
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DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
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DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
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DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8),
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/* Core output clk */
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DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
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DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
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dtable_3b, CLK_DIVIDER_HIWORD_MASK),
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DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
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DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8,
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DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK),
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};
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static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
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DEF_MOD("gic", R9A07G044_CLK_GIC600,
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R9A07G044_CLK_P1,
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0x514, BIT(0), (BIT(0) | BIT(1))),
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DEF_MOD("ia55", R9A07G044_CLK_IA55,
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R9A07G044_CLK_P1,
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0x518, (BIT(0) | BIT(1)), BIT(0)),
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DEF_MOD("scif0", R9A07G044_CLK_SCIF0,
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R9A07G044_CLK_P0,
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0x584, BIT(0), BIT(0)),
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DEF_MOD("scif1", R9A07G044_CLK_SCIF1,
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R9A07G044_CLK_P0,
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0x584, BIT(1), BIT(1)),
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DEF_MOD("scif2", R9A07G044_CLK_SCIF2,
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R9A07G044_CLK_P0,
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0x584, BIT(2), BIT(2)),
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DEF_MOD("scif3", R9A07G044_CLK_SCIF3,
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R9A07G044_CLK_P0,
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0x584, BIT(3), BIT(3)),
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DEF_MOD("scif4", R9A07G044_CLK_SCIF4,
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R9A07G044_CLK_P0,
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0x584, BIT(4), BIT(4)),
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DEF_MOD("sci0", R9A07G044_CLK_SCI0,
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R9A07G044_CLK_P0,
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0x588, BIT(0), BIT(0)),
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};
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static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
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MOD_CLK_BASE + R9A07G044_CLK_GIC600,
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};
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const struct rzg2l_cpg_info r9a07g044_cpg_info = {
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/* Core Clocks */
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.core_clks = r9a07g044_core_clks,
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.num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Critical Module Clocks */
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.crit_mod_clks = r9a07g044_crit_mod_clks,
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.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
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/* Module Clocks */
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.mod_clks = r9a07g044_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
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.num_hw_mod_clks = R9A07G044_CLK_MIPI_DSI_PIN + 1,
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};
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