183 lines
4.1 KiB
C
183 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012-2013 Avionic Design GmbH
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* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
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*
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* Based on the KMS/FB DMA helpers
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* Copyright (C) 2012 Analog Devices Inc.
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*/
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#include <linux/console.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_framebuffer.h>
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#include <drm/drm_gem_framebuffer_helper.h>
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#include <drm/drm_modeset_helper.h>
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#include "drm.h"
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#include "gem.h"
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struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer,
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unsigned int index)
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{
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return to_tegra_bo(drm_gem_fb_get_obj(framebuffer, index));
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}
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bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer)
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{
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struct tegra_bo *bo = tegra_fb_get_plane(framebuffer, 0);
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if (bo->flags & TEGRA_BO_BOTTOM_UP)
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return true;
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return false;
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}
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int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
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struct tegra_bo_tiling *tiling)
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{
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uint64_t modifier = framebuffer->modifier;
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if (fourcc_mod_is_vendor(modifier, NVIDIA)) {
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if ((modifier & DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT) == 0)
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tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_TEGRA;
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else
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tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_GPU;
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modifier &= ~DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT;
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}
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switch (modifier) {
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case DRM_FORMAT_MOD_LINEAR:
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tiling->mode = TEGRA_BO_TILING_MODE_PITCH;
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tiling->value = 0;
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break;
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case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED:
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tiling->mode = TEGRA_BO_TILING_MODE_TILED;
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tiling->value = 0;
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break;
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case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0):
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tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
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tiling->value = 0;
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break;
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case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1):
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tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
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tiling->value = 1;
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break;
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case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2):
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tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
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tiling->value = 2;
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break;
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case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3):
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tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
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tiling->value = 3;
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break;
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case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4):
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tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
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tiling->value = 4;
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break;
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case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5):
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tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
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tiling->value = 5;
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break;
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default:
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DRM_DEBUG_KMS("unknown format modifier: %llx\n", modifier);
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return -EINVAL;
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}
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return 0;
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}
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static const struct drm_framebuffer_funcs tegra_fb_funcs = {
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.destroy = drm_gem_fb_destroy,
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.create_handle = drm_gem_fb_create_handle,
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};
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struct drm_framebuffer *tegra_fb_alloc(struct drm_device *drm,
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const struct drm_mode_fb_cmd2 *mode_cmd,
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struct tegra_bo **planes,
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unsigned int num_planes)
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{
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struct drm_framebuffer *fb;
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unsigned int i;
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int err;
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fb = kzalloc(sizeof(*fb), GFP_KERNEL);
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if (!fb)
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return ERR_PTR(-ENOMEM);
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drm_helper_mode_fill_fb_struct(drm, fb, mode_cmd);
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for (i = 0; i < fb->format->num_planes; i++)
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fb->obj[i] = &planes[i]->gem;
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err = drm_framebuffer_init(drm, fb, &tegra_fb_funcs);
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if (err < 0) {
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dev_err(drm->dev, "failed to initialize framebuffer: %d\n",
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err);
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kfree(fb);
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return ERR_PTR(err);
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}
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return fb;
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}
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struct drm_framebuffer *tegra_fb_create(struct drm_device *drm,
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struct drm_file *file,
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const struct drm_mode_fb_cmd2 *cmd)
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{
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const struct drm_format_info *info = drm_get_format_info(drm, cmd);
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struct tegra_bo *planes[4];
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struct drm_gem_object *gem;
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struct drm_framebuffer *fb;
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unsigned int i;
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int err;
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for (i = 0; i < info->num_planes; i++) {
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unsigned int width = cmd->width / (i ? info->hsub : 1);
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unsigned int height = cmd->height / (i ? info->vsub : 1);
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unsigned int size, bpp;
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gem = drm_gem_object_lookup(file, cmd->handles[i]);
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if (!gem) {
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err = -ENXIO;
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goto unreference;
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}
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bpp = info->cpp[i];
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size = (height - 1) * cmd->pitches[i] +
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width * bpp + cmd->offsets[i];
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if (gem->size < size) {
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err = -EINVAL;
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drm_gem_object_put(gem);
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goto unreference;
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}
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planes[i] = to_tegra_bo(gem);
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}
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fb = tegra_fb_alloc(drm, cmd, planes, i);
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if (IS_ERR(fb)) {
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err = PTR_ERR(fb);
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goto unreference;
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}
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return fb;
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unreference:
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while (i--)
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drm_gem_object_put(&planes[i]->gem);
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return ERR_PTR(err);
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}
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