96 lines
2.0 KiB
ArmAsm
96 lines
2.0 KiB
ArmAsm
/*
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* Copyright 2013, Michael (Ellerman|Neuling), IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/asm-offsets.h>
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#include <asm/ppc_asm.h>
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#include <asm/reg.h>
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#include "subcore.h"
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_GLOBAL(split_core_secondary_loop)
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/*
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* r3 = u8 *state, used throughout the routine
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* r4 = temp
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* r5 = temp
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* ..
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* r12 = MSR
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*/
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mfmsr r12
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/* Disable interrupts so SRR0/1 don't get trashed */
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li r4,0
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ori r4,r4,MSR_EE|MSR_SE|MSR_BE|MSR_RI
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andc r4,r12,r4
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sync
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mtmsrd r4
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/* Switch to real mode and leave interrupts off */
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li r5, MSR_IR|MSR_DR
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andc r5, r4, r5
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LOAD_REG_ADDR(r4, real_mode)
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mtspr SPRN_SRR0,r4
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mtspr SPRN_SRR1,r5
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rfid
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b . /* prevent speculative execution */
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real_mode:
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/* Grab values from unsplit SPRs */
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mfspr r6, SPRN_LDBAR
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mfspr r7, SPRN_PMMAR
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mfspr r8, SPRN_PMCR
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mfspr r9, SPRN_RPR
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mfspr r10, SPRN_SDR1
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/* Order reading the SPRs vs telling the primary we are ready to split */
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sync
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/* Tell thread 0 we are in real mode */
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li r4, SYNC_STEP_REAL_MODE
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stb r4, 0(r3)
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li r5, (HID0_POWER8_4LPARMODE | HID0_POWER8_2LPARMODE)@highest
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sldi r5, r5, 48
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/* Loop until we see the split happen in HID0 */
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1: mfspr r4, SPRN_HID0
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and. r4, r4, r5
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beq 1b
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/*
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* We only need to initialise the below regs once for each subcore,
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* but it's simpler and harmless to do it on each thread.
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*/
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/* Make sure various SPRS have sane values */
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li r4, 0
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mtspr SPRN_LPID, r4
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mtspr SPRN_PCR, r4
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mtspr SPRN_HDEC, r4
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/* Restore SPR values now we are split */
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mtspr SPRN_LDBAR, r6
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mtspr SPRN_PMMAR, r7
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mtspr SPRN_PMCR, r8
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mtspr SPRN_RPR, r9
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mtspr SPRN_SDR1, r10
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LOAD_REG_ADDR(r5, virtual_mode)
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/* Get out of real mode */
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mtspr SPRN_SRR0,r5
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mtspr SPRN_SRR1,r12
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rfid
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b . /* prevent speculative execution */
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virtual_mode:
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blr
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