304 lines
8.4 KiB
C
304 lines
8.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2018 Intel Corporation. All rights reserved.
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*/
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#ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
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#define __INCLUDE_SOUND_SOF_TOPOLOGY_H__
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#include <sound/sof/header.h>
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/*
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* Component
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*/
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/* types of component */
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enum sof_comp_type {
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SOF_COMP_NONE = 0,
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SOF_COMP_HOST,
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SOF_COMP_DAI,
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SOF_COMP_SG_HOST, /**< scatter gather variant */
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SOF_COMP_SG_DAI, /**< scatter gather variant */
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SOF_COMP_VOLUME,
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SOF_COMP_MIXER,
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SOF_COMP_MUX,
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SOF_COMP_SRC,
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SOF_COMP_SPLITTER,
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SOF_COMP_TONE,
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SOF_COMP_SWITCH,
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SOF_COMP_BUFFER,
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SOF_COMP_EQ_IIR,
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SOF_COMP_EQ_FIR,
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SOF_COMP_KEYWORD_DETECT,
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SOF_COMP_KPB, /* A key phrase buffer component */
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SOF_COMP_SELECTOR, /**< channel selector component */
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SOF_COMP_DEMUX,
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SOF_COMP_ASRC, /**< Asynchronous sample rate converter */
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SOF_COMP_DCBLOCK,
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SOF_COMP_SMART_AMP, /**< smart amplifier component */
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/* keep FILEREAD/FILEWRITE as the last ones */
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SOF_COMP_FILEREAD = 10000, /**< host test based file IO */
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SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */
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};
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/* XRUN action for component */
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#define SOF_XRUN_STOP 1 /**< stop stream */
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#define SOF_XRUN_UNDER_ZERO 2 /**< send 0s to sink */
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#define SOF_XRUN_OVER_NULL 4 /**< send data to NULL */
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/* create new generic component - SOF_IPC_TPLG_COMP_NEW */
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struct sof_ipc_comp {
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struct sof_ipc_cmd_hdr hdr;
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uint32_t id;
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enum sof_comp_type type;
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uint32_t pipeline_id;
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uint32_t core;
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/* reserved for future use */
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uint32_t reserved[1];
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} __packed;
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/*
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* Component Buffers
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*/
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/*
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* SOF memory capabilities, add new ones at the end
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*/
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#define SOF_MEM_CAPS_RAM (1 << 0)
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#define SOF_MEM_CAPS_ROM (1 << 1)
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#define SOF_MEM_CAPS_EXT (1 << 2) /**< external */
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#define SOF_MEM_CAPS_LP (1 << 3) /**< low power */
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#define SOF_MEM_CAPS_HP (1 << 4) /**< high performance */
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#define SOF_MEM_CAPS_DMA (1 << 5) /**< DMA'able */
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#define SOF_MEM_CAPS_CACHE (1 << 6) /**< cacheable */
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#define SOF_MEM_CAPS_EXEC (1 << 7) /**< executable */
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/*
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* overrun will cause ring buffer overwrite, instead of XRUN.
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*/
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#define SOF_BUF_OVERRUN_PERMITTED BIT(0)
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/*
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* underrun will cause readback of 0s, instead of XRUN.
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*/
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#define SOF_BUF_UNDERRUN_PERMITTED BIT(1)
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/* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
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struct sof_ipc_buffer {
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struct sof_ipc_comp comp;
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uint32_t size; /**< buffer size in bytes */
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uint32_t caps; /**< SOF_MEM_CAPS_ */
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uint32_t flags; /**< SOF_BUF_ flags defined above */
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uint32_t reserved; /**< reserved for future use */
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} __packed;
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/* generic component config data - must always be after struct sof_ipc_comp */
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struct sof_ipc_comp_config {
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struct sof_ipc_cmd_hdr hdr;
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uint32_t periods_sink; /**< 0 means variable */
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uint32_t periods_source;/**< 0 means variable */
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uint32_t reserved1; /**< reserved */
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uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */
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uint32_t xrun_action;
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/* reserved for future use */
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uint32_t reserved[2];
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} __packed;
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/* generic host component */
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struct sof_ipc_comp_host {
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struct sof_ipc_comp comp;
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struct sof_ipc_comp_config config;
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uint32_t direction; /**< SOF_IPC_STREAM_ */
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uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */
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uint32_t dmac_config; /**< DMA engine specific */
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} __packed;
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/* generic DAI component */
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struct sof_ipc_comp_dai {
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struct sof_ipc_comp comp;
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struct sof_ipc_comp_config config;
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uint32_t direction; /**< SOF_IPC_STREAM_ */
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uint32_t dai_index; /**< index of this type dai */
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uint32_t type; /**< DAI type - SOF_DAI_ */
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uint32_t reserved; /**< reserved */
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} __packed;
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/* generic mixer component */
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struct sof_ipc_comp_mixer {
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struct sof_ipc_comp comp;
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struct sof_ipc_comp_config config;
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} __packed;
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/* volume ramping types */
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enum sof_volume_ramp {
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SOF_VOLUME_LINEAR = 0,
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SOF_VOLUME_LOG,
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SOF_VOLUME_LINEAR_ZC,
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SOF_VOLUME_LOG_ZC,
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};
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/* generic volume component */
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struct sof_ipc_comp_volume {
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struct sof_ipc_comp comp;
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struct sof_ipc_comp_config config;
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uint32_t channels;
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uint32_t min_value;
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uint32_t max_value;
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uint32_t ramp; /**< SOF_VOLUME_ */
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uint32_t initial_ramp; /**< ramp space in ms */
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} __packed;
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/* generic SRC component */
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struct sof_ipc_comp_src {
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struct sof_ipc_comp comp;
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struct sof_ipc_comp_config config;
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/* either source or sink rate must be non zero */
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uint32_t source_rate; /**< source rate or 0 for variable */
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uint32_t sink_rate; /**< sink rate or 0 for variable */
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uint32_t rate_mask; /**< SOF_RATE_ supported rates */
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} __packed;
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/* generic ASRC component */
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struct sof_ipc_comp_asrc {
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struct sof_ipc_comp comp;
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struct sof_ipc_comp_config config;
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/* either source or sink rate must be non zero */
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uint32_t source_rate; /**< Define fixed source rate or */
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/**< use 0 to indicate need to get */
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/**< the rate from stream */
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uint32_t sink_rate; /**< Define fixed sink rate or */
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/**< use 0 to indicate need to get */
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/**< the rate from stream */
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uint32_t asynchronous_mode; /**< synchronous 0, asynchronous 1 */
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/**< When 1 the ASRC tracks and */
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/**< compensates for drift. */
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uint32_t operation_mode; /**< push 0, pull 1, In push mode the */
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/**< ASRC consumes a defined number */
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/**< of frames at input, with varying */
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/**< number of frames at output. */
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/**< In pull mode the ASRC outputs */
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/**< a defined number of frames while */
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/**< number of input frames varies. */
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/* reserved for future use */
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uint32_t reserved[4];
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} __attribute__((packed));
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/* generic MUX component */
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struct sof_ipc_comp_mux {
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struct sof_ipc_comp comp;
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struct sof_ipc_comp_config config;
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} __packed;
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/* generic tone generator component */
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struct sof_ipc_comp_tone {
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struct sof_ipc_comp comp;
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struct sof_ipc_comp_config config;
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int32_t sample_rate;
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int32_t frequency;
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int32_t amplitude;
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int32_t freq_mult;
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int32_t ampl_mult;
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int32_t length;
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int32_t period;
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int32_t repeats;
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int32_t ramp_step;
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} __packed;
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/** \brief Types of processing components */
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enum sof_ipc_process_type {
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SOF_PROCESS_NONE = 0, /**< None */
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SOF_PROCESS_EQFIR, /**< Intel FIR */
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SOF_PROCESS_EQIIR, /**< Intel IIR */
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SOF_PROCESS_KEYWORD_DETECT, /**< Keyword Detection */
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SOF_PROCESS_KPB, /**< KeyPhrase Buffer Manager */
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SOF_PROCESS_CHAN_SELECTOR, /**< Channel Selector */
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SOF_PROCESS_MUX,
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SOF_PROCESS_DEMUX,
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SOF_PROCESS_DCBLOCK,
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SOF_PROCESS_SMART_AMP, /**< Smart Amplifier */
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};
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/* generic "effect", "codec" or proprietary processing component */
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struct sof_ipc_comp_process {
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struct sof_ipc_comp comp;
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struct sof_ipc_comp_config config;
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uint32_t size; /**< size of bespoke data section in bytes */
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uint32_t type; /**< sof_ipc_process_type */
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/* reserved for future use */
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uint32_t reserved[7];
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uint8_t data[0];
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} __packed;
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/* frees components, buffers and pipelines
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* SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE
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*/
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struct sof_ipc_free {
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struct sof_ipc_cmd_hdr hdr;
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uint32_t id;
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} __packed;
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struct sof_ipc_comp_reply {
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struct sof_ipc_reply rhdr;
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uint32_t id;
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uint32_t offset;
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} __packed;
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/*
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* Pipeline
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*/
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/** \brief Types of pipeline scheduling time domains */
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enum sof_ipc_pipe_sched_time_domain {
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SOF_TIME_DOMAIN_DMA = 0, /**< DMA interrupt */
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SOF_TIME_DOMAIN_TIMER, /**< Timer interrupt */
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};
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/* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
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struct sof_ipc_pipe_new {
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struct sof_ipc_cmd_hdr hdr;
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uint32_t comp_id; /**< component id for pipeline */
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uint32_t pipeline_id; /**< pipeline id */
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uint32_t sched_id; /**< Scheduling component id */
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uint32_t core; /**< core we run on */
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uint32_t period; /**< execution period in us*/
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uint32_t priority; /**< priority level 0 (low) to 10 (max) */
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uint32_t period_mips; /**< worst case instruction count per period */
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uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */
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uint32_t xrun_limit_usecs; /**< report xruns greater than limit */
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uint32_t time_domain; /**< scheduling time domain */
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} __packed;
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/* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */
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struct sof_ipc_pipe_ready {
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struct sof_ipc_cmd_hdr hdr;
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uint32_t comp_id;
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} __packed;
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struct sof_ipc_pipe_free {
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struct sof_ipc_cmd_hdr hdr;
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uint32_t comp_id;
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} __packed;
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/* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */
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struct sof_ipc_pipe_comp_connect {
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struct sof_ipc_cmd_hdr hdr;
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uint32_t source_id;
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uint32_t sink_id;
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} __packed;
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/* external events */
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enum sof_event_types {
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SOF_EVENT_NONE = 0,
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SOF_KEYWORD_DETECT_DAPM_EVENT,
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};
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#endif
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