346 lines
12 KiB
C
346 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Functions to access TPS65219 Power Management IC.
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*
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* Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
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*/
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#ifndef MFD_TPS65219_H
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#define MFD_TPS65219_H
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#include <linux/bitops.h>
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#include <linux/notifier.h>
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#include <linux/regulator/driver.h>
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struct regmap;
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struct regmap_irq_chip_data;
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#define TPS65219_1V35 1350000
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#define TPS65219_1V8 1800000
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/* TPS chip id list */
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#define TPS65219 0xF0
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/* I2C ID for TPS65219 part */
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#define TPS65219_I2C_ID 0x24
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/* All register addresses */
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#define TPS65219_REG_TI_DEV_ID 0x00
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#define TPS65219_REG_NVM_ID 0x01
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#define TPS65219_REG_ENABLE_CTRL 0x02
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#define TPS65219_REG_BUCKS_CONFIG 0x03
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#define TPS65219_REG_LDO4_VOUT 0x04
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#define TPS65219_REG_LDO3_VOUT 0x05
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#define TPS65219_REG_LDO2_VOUT 0x06
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#define TPS65219_REG_LDO1_VOUT 0x07
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#define TPS65219_REG_BUCK3_VOUT 0x8
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#define TPS65219_REG_BUCK2_VOUT 0x9
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#define TPS65219_REG_BUCK1_VOUT 0xA
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#define TPS65219_REG_LDO4_SEQUENCE_SLOT 0xB
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#define TPS65219_REG_LDO3_SEQUENCE_SLOT 0xC
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#define TPS65219_REG_LDO2_SEQUENCE_SLOT 0xD
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#define TPS65219_REG_LDO1_SEQUENCE_SLOT 0xE
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#define TPS65219_REG_BUCK3_SEQUENCE_SLOT 0xF
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#define TPS65219_REG_BUCK2_SEQUENCE_SLOT 0x10
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#define TPS65219_REG_BUCK1_SEQUENCE_SLOT 0x11
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#define TPS65219_REG_nRST_SEQUENCE_SLOT 0x12
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#define TPS65219_REG_GPIO_SEQUENCE_SLOT 0x13
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#define TPS65219_REG_GPO2_SEQUENCE_SLOT 0x14
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#define TPS65219_REG_GPO1_SEQUENCE_SLOT 0x15
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#define TPS65219_REG_POWER_UP_SLOT_DURATION_1 0x16
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#define TPS65219_REG_POWER_UP_SLOT_DURATION_2 0x17
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#define TPS65219_REG_POWER_UP_SLOT_DURATION_3 0x18
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#define TPS65219_REG_POWER_UP_SLOT_DURATION_4 0x19
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#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_1 0x1A
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#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_2 0x1B
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#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_3 0x1C
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#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_4 0x1D
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#define TPS65219_REG_GENERAL_CONFIG 0x1E
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#define TPS65219_REG_MFP_1_CONFIG 0x1F
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#define TPS65219_REG_MFP_2_CONFIG 0x20
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#define TPS65219_REG_STBY_1_CONFIG 0x21
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#define TPS65219_REG_STBY_2_CONFIG 0x22
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#define TPS65219_REG_OC_DEGL_CONFIG 0x23
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/* 'sub irq' MASK registers */
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#define TPS65219_REG_INT_MASK_UV 0x24
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#define TPS65219_REG_MASK_CONFIG 0x25
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#define TPS65219_REG_I2C_ADDRESS_REG 0x26
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#define TPS65219_REG_USER_GENERAL_NVM_STORAGE 0x27
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#define TPS65219_REG_MANUFACTURING_VER 0x28
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#define TPS65219_REG_MFP_CTRL 0x29
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#define TPS65219_REG_DISCHARGE_CONFIG 0x2A
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/* main irq registers */
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#define TPS65219_REG_INT_SOURCE 0x2B
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/* 'sub irq' registers */
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#define TPS65219_REG_INT_LDO_3_4 0x2C
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#define TPS65219_REG_INT_LDO_1_2 0x2D
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#define TPS65219_REG_INT_BUCK_3 0x2E
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#define TPS65219_REG_INT_BUCK_1_2 0x2F
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#define TPS65219_REG_INT_SYSTEM 0x30
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#define TPS65219_REG_INT_RV 0x31
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#define TPS65219_REG_INT_TIMEOUT_RV_SD 0x32
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#define TPS65219_REG_INT_PB 0x33
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#define TPS65219_REG_INT_LDO_3_4_POS 0
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#define TPS65219_REG_INT_LDO_1_2_POS 1
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#define TPS65219_REG_INT_BUCK_3_POS 2
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#define TPS65219_REG_INT_BUCK_1_2_POS 3
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#define TPS65219_REG_INT_SYS_POS 4
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#define TPS65219_REG_INT_RV_POS 5
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#define TPS65219_REG_INT_TO_RV_POS 6
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#define TPS65219_REG_INT_PB_POS 7
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#define TPS65219_REG_USER_NVM_CMD 0x34
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#define TPS65219_REG_POWER_UP_STATUS 0x35
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#define TPS65219_REG_SPARE_2 0x36
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#define TPS65219_REG_SPARE_3 0x37
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#define TPS65219_REG_FACTORY_CONFIG_2 0x41
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/* Register field definitions */
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#define TPS65219_DEVID_REV_MASK GENMASK(7, 0)
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#define TPS65219_BUCKS_LDOS_VOUT_VSET_MASK GENMASK(5, 0)
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#define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6)
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#define TPS65219_BUCKS_BW_SEL_MASK BIT(7)
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#define LDO_BYP_SHIFT 6
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#define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT)
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#define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7)
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/* Regulators enable control */
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#define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0)
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#define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1)
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#define TPS65219_ENABLE_BUCK3_EN_MASK BIT(2)
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#define TPS65219_ENABLE_LDO1_EN_MASK BIT(3)
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#define TPS65219_ENABLE_LDO2_EN_MASK BIT(4)
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#define TPS65219_ENABLE_LDO3_EN_MASK BIT(5)
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#define TPS65219_ENABLE_LDO4_EN_MASK BIT(6)
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/* power ON-OFF sequence slot */
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#define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0)
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#define TPS65219_BUCKS_LDOS_SEQUENCE_ON_SLOT_MASK GENMASK(7, 4)
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/* TODO: Not needed, same mapping as TPS65219_ENABLE_REGNAME_EN, factorize */
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#define TPS65219_STBY1_BUCK1_STBY_EN_MASK BIT(0)
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#define TPS65219_STBY1_BUCK2_STBY_EN_MASK BIT(1)
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#define TPS65219_STBY1_BUCK3_STBY_EN_MASK BIT(2)
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#define TPS65219_STBY1_LDO1_STBY_EN_MASK BIT(3)
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#define TPS65219_STBY1_LDO2_STBY_EN_MASK BIT(4)
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#define TPS65219_STBY1_LDO3_STBY_EN_MASK BIT(5)
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#define TPS65219_STBY1_LDO4_STBY_EN_MASK BIT(6)
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/* STBY_2 config */
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#define TPS65219_STBY2_GPO1_STBY_EN_MASK BIT(0)
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#define TPS65219_STBY2_GPO2_STBY_EN_MASK BIT(1)
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#define TPS65219_STBY2_GPIO_STBY_EN_MASK BIT(2)
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/* MFP Control */
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#define TPS65219_MFP_I2C_OFF_REQ_MASK BIT(0)
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#define TPS65219_MFP_STBY_I2C_CTRL_MASK BIT(1)
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#define TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK BIT(2)
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#define TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK BIT(3)
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#define TPS65219_MFP_GPIO_STATUS_MASK BIT(4)
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/* MFP_1 Config */
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#define TPS65219_MFP_1_VSEL_DDR_SEL_MASK BIT(0)
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#define TPS65219_MFP_1_VSEL_SD_POL_MASK BIT(1)
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#define TPS65219_MFP_1_VSEL_RAIL_MASK BIT(2)
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/* MFP_2 Config */
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#define TPS65219_MFP_2_MODE_STBY_MASK GENMASK(1, 0)
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#define TPS65219_MFP_2_MODE_RESET_MASK BIT(2)
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#define TPS65219_MFP_2_EN_PB_VSENSE_DEGL_MASK BIT(3)
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#define TPS65219_MFP_2_EN_PB_VSENSE_MASK GENMASK(5, 4)
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#define TPS65219_MFP_2_WARM_COLD_RESET_MASK BIT(6)
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#define TPS65219_MFP_2_PU_ON_FSD_MASK BIT(7)
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#define TPS65219_MFP_2_EN 0
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#define TPS65219_MFP_2_PB BIT(4)
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#define TPS65219_MFP_2_VSENSE BIT(5)
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/* MASK_UV Config */
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#define TPS65219_REG_MASK_UV_LDO1_UV_MASK BIT(0)
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#define TPS65219_REG_MASK_UV_LDO2_UV_MASK BIT(1)
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#define TPS65219_REG_MASK_UV_LDO3_UV_MASK BIT(2)
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#define TPS65219_REG_MASK_UV_LDO4_UV_MASK BIT(3)
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#define TPS65219_REG_MASK_UV_BUCK1_UV_MASK BIT(4)
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#define TPS65219_REG_MASK_UV_BUCK2_UV_MASK BIT(5)
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#define TPS65219_REG_MASK_UV_BUCK3_UV_MASK BIT(6)
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#define TPS65219_REG_MASK_UV_RETRY_MASK BIT(7)
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/* MASK Config */
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// SENSOR_N_WARM_MASK already defined in Thermal
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#define TPS65219_REG_MASK_INT_FOR_RV_MASK BIT(4)
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#define TPS65219_REG_MASK_EFFECT_MASK GENMASK(2, 1)
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#define TPS65219_REG_MASK_INT_FOR_PB_MASK BIT(7)
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/* UnderVoltage - Short to GND - OverCurrent*/
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/* LDO3-4 */
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#define TPS65219_INT_LDO3_SCG_MASK BIT(0)
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#define TPS65219_INT_LDO3_OC_MASK BIT(1)
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#define TPS65219_INT_LDO3_UV_MASK BIT(2)
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#define TPS65219_INT_LDO4_SCG_MASK BIT(3)
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#define TPS65219_INT_LDO4_OC_MASK BIT(4)
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#define TPS65219_INT_LDO4_UV_MASK BIT(5)
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/* LDO1-2 */
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#define TPS65219_INT_LDO1_SCG_MASK BIT(0)
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#define TPS65219_INT_LDO1_OC_MASK BIT(1)
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#define TPS65219_INT_LDO1_UV_MASK BIT(2)
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#define TPS65219_INT_LDO2_SCG_MASK BIT(3)
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#define TPS65219_INT_LDO2_OC_MASK BIT(4)
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#define TPS65219_INT_LDO2_UV_MASK BIT(5)
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/* BUCK3 */
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#define TPS65219_INT_BUCK3_SCG_MASK BIT(0)
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#define TPS65219_INT_BUCK3_OC_MASK BIT(1)
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#define TPS65219_INT_BUCK3_NEG_OC_MASK BIT(2)
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#define TPS65219_INT_BUCK3_UV_MASK BIT(3)
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/* BUCK1-2 */
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#define TPS65219_INT_BUCK1_SCG_MASK BIT(0)
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#define TPS65219_INT_BUCK1_OC_MASK BIT(1)
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#define TPS65219_INT_BUCK1_NEG_OC_MASK BIT(2)
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#define TPS65219_INT_BUCK1_UV_MASK BIT(3)
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#define TPS65219_INT_BUCK2_SCG_MASK BIT(4)
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#define TPS65219_INT_BUCK2_OC_MASK BIT(5)
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#define TPS65219_INT_BUCK2_NEG_OC_MASK BIT(6)
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#define TPS65219_INT_BUCK2_UV_MASK BIT(7)
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/* Thermal Sensor */
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#define TPS65219_INT_SENSOR_3_WARM_MASK BIT(0)
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#define TPS65219_INT_SENSOR_2_WARM_MASK BIT(1)
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#define TPS65219_INT_SENSOR_1_WARM_MASK BIT(2)
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#define TPS65219_INT_SENSOR_0_WARM_MASK BIT(3)
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#define TPS65219_INT_SENSOR_3_HOT_MASK BIT(4)
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#define TPS65219_INT_SENSOR_2_HOT_MASK BIT(5)
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#define TPS65219_INT_SENSOR_1_HOT_MASK BIT(6)
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#define TPS65219_INT_SENSOR_0_HOT_MASK BIT(7)
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/* Residual Voltage */
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#define TPS65219_INT_BUCK1_RV_MASK BIT(0)
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#define TPS65219_INT_BUCK2_RV_MASK BIT(1)
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#define TPS65219_INT_BUCK3_RV_MASK BIT(2)
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#define TPS65219_INT_LDO1_RV_MASK BIT(3)
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#define TPS65219_INT_LDO2_RV_MASK BIT(4)
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#define TPS65219_INT_LDO3_RV_MASK BIT(5)
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#define TPS65219_INT_LDO4_RV_MASK BIT(6)
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/* Residual Voltage ShutDown */
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#define TPS65219_INT_BUCK1_RV_SD_MASK BIT(0)
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#define TPS65219_INT_BUCK2_RV_SD_MASK BIT(1)
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#define TPS65219_INT_BUCK3_RV_SD_MASK BIT(2)
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#define TPS65219_INT_LDO1_RV_SD_MASK BIT(3)
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#define TPS65219_INT_LDO2_RV_SD_MASK BIT(4)
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#define TPS65219_INT_LDO3_RV_SD_MASK BIT(5)
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#define TPS65219_INT_LDO4_RV_SD_MASK BIT(6)
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#define TPS65219_INT_TIMEOUT_MASK BIT(7)
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/* Power Button */
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#define TPS65219_INT_PB_FALLING_EDGE_DETECT_MASK BIT(0)
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#define TPS65219_INT_PB_RISING_EDGE_DETECT_MASK BIT(1)
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#define TPS65219_INT_PB_REAL_TIME_STATUS_MASK BIT(2)
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#define TPS65219_PB_POS 7
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#define TPS65219_TO_RV_POS 6
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#define TPS65219_RV_POS 5
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#define TPS65219_SYS_POS 4
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#define TPS65219_BUCK_1_2_POS 3
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#define TPS65219_BUCK_3_POS 2
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#define TPS65219_LDO_1_2_POS 1
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#define TPS65219_LDO_3_4_POS 0
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/* IRQs */
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enum {
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/* LDO3-4 register IRQs */
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TPS65219_INT_LDO3_SCG,
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TPS65219_INT_LDO3_OC,
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TPS65219_INT_LDO3_UV,
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TPS65219_INT_LDO4_SCG,
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TPS65219_INT_LDO4_OC,
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TPS65219_INT_LDO4_UV,
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/* LDO1-2 */
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TPS65219_INT_LDO1_SCG,
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TPS65219_INT_LDO1_OC,
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TPS65219_INT_LDO1_UV,
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TPS65219_INT_LDO2_SCG,
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TPS65219_INT_LDO2_OC,
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TPS65219_INT_LDO2_UV,
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/* BUCK3 */
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TPS65219_INT_BUCK3_SCG,
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TPS65219_INT_BUCK3_OC,
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TPS65219_INT_BUCK3_NEG_OC,
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TPS65219_INT_BUCK3_UV,
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/* BUCK1-2 */
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TPS65219_INT_BUCK1_SCG,
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TPS65219_INT_BUCK1_OC,
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TPS65219_INT_BUCK1_NEG_OC,
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TPS65219_INT_BUCK1_UV,
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TPS65219_INT_BUCK2_SCG,
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TPS65219_INT_BUCK2_OC,
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TPS65219_INT_BUCK2_NEG_OC,
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TPS65219_INT_BUCK2_UV,
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/* Thermal Sensor */
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TPS65219_INT_SENSOR_3_WARM,
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TPS65219_INT_SENSOR_2_WARM,
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TPS65219_INT_SENSOR_1_WARM,
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TPS65219_INT_SENSOR_0_WARM,
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TPS65219_INT_SENSOR_3_HOT,
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TPS65219_INT_SENSOR_2_HOT,
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TPS65219_INT_SENSOR_1_HOT,
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TPS65219_INT_SENSOR_0_HOT,
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/* Residual Voltage */
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TPS65219_INT_BUCK1_RV,
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TPS65219_INT_BUCK2_RV,
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TPS65219_INT_BUCK3_RV,
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TPS65219_INT_LDO1_RV,
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TPS65219_INT_LDO2_RV,
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TPS65219_INT_LDO3_RV,
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TPS65219_INT_LDO4_RV,
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/* Residual Voltage ShutDown */
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TPS65219_INT_BUCK1_RV_SD,
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TPS65219_INT_BUCK2_RV_SD,
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TPS65219_INT_BUCK3_RV_SD,
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TPS65219_INT_LDO1_RV_SD,
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TPS65219_INT_LDO2_RV_SD,
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TPS65219_INT_LDO3_RV_SD,
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TPS65219_INT_LDO4_RV_SD,
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TPS65219_INT_TIMEOUT,
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/* Power Button */
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TPS65219_INT_PB_FALLING_EDGE_DETECT,
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TPS65219_INT_PB_RISING_EDGE_DETECT,
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};
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enum tps65219_regulator_id {
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/* DCDC's */
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TPS65219_BUCK_1,
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TPS65219_BUCK_2,
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TPS65219_BUCK_3,
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/* LDOs */
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TPS65219_LDO_1,
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TPS65219_LDO_2,
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TPS65219_LDO_3,
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TPS65219_LDO_4,
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};
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/* Number of step-down converters available */
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#define TPS65219_NUM_DCDC 3
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/* Number of LDO voltage regulators available */
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#define TPS65219_NUM_LDO 4
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/* Number of total regulators available */
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#define TPS65219_NUM_REGULATOR (TPS65219_NUM_DCDC + TPS65219_NUM_LDO)
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/* Define the TPS65219 IRQ numbers */
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enum tps65219_irqs {
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/* INT source registers */
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TPS65219_TO_RV_SD_SET_IRQ,
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TPS65219_RV_SET_IRQ,
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TPS65219_SYS_SET_IRQ,
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TPS65219_BUCK_1_2_SET_IRQ,
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TPS65219_BUCK_3_SET_IRQ,
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TPS65219_LDO_1_2_SET_IRQ,
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TPS65219_LDO_3_4_SET_IRQ,
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TPS65219_PB_SET_IRQ,
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};
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/**
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* struct tps65219 - tps65219 sub-driver chip access routines
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*
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* Device data may be used to access the TPS65219 chip
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*
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* @dev: MFD device
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* @regmap: Regmap for accessing the device registers
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* @irq_data: Regmap irq data used for the irq chip
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* @nb: notifier block for the restart handler
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*/
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struct tps65219 {
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struct device *dev;
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struct regmap *regmap;
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struct regmap_irq_chip_data *irq_data;
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struct notifier_block nb;
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};
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#endif /* MFD_TPS65219_H */
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