309 lines
9.8 KiB
C
309 lines
9.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Intel MAX 10 Board Management Controller chip.
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*
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* Copyright (C) 2018-2020 Intel Corporation, Inc.
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*/
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#ifndef __MFD_INTEL_M10_BMC_H
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#define __MFD_INTEL_M10_BMC_H
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/dev_printk.h>
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#include <linux/regmap.h>
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#include <linux/rwsem.h>
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#define M10BMC_N3000_LEGACY_BUILD_VER 0x300468
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#define M10BMC_N3000_SYS_BASE 0x300800
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#define M10BMC_N3000_SYS_END 0x300fff
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#define M10BMC_N3000_FLASH_BASE 0x10000000
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#define M10BMC_N3000_FLASH_END 0x1fffffff
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#define M10BMC_N3000_MEM_END M10BMC_N3000_FLASH_END
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#define M10BMC_STAGING_BASE 0x18000000
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#define M10BMC_STAGING_SIZE 0x3800000
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/* Register offset of system registers */
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#define NIOS2_N3000_FW_VERSION 0x0
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#define M10BMC_N3000_MAC_LOW 0x10
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#define M10BMC_N3000_MAC_BYTE4 GENMASK(7, 0)
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#define M10BMC_N3000_MAC_BYTE3 GENMASK(15, 8)
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#define M10BMC_N3000_MAC_BYTE2 GENMASK(23, 16)
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#define M10BMC_N3000_MAC_BYTE1 GENMASK(31, 24)
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#define M10BMC_N3000_MAC_HIGH 0x14
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#define M10BMC_N3000_MAC_BYTE6 GENMASK(7, 0)
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#define M10BMC_N3000_MAC_BYTE5 GENMASK(15, 8)
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#define M10BMC_N3000_MAC_COUNT GENMASK(23, 16)
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#define M10BMC_N3000_TEST_REG 0x3c
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#define M10BMC_N3000_BUILD_VER 0x68
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#define M10BMC_N3000_VER_MAJOR_MSK GENMASK(23, 16)
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#define M10BMC_N3000_VER_PCB_INFO_MSK GENMASK(31, 24)
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#define M10BMC_N3000_VER_LEGACY_INVALID 0xffffffff
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/* Telemetry registers */
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#define M10BMC_N3000_TELEM_START 0x100
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#define M10BMC_N3000_TELEM_END 0x250
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#define M10BMC_D5005_TELEM_END 0x300
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/* Secure update doorbell register, in system register region */
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#define M10BMC_N3000_DOORBELL 0x400
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/* Authorization Result register, in system register region */
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#define M10BMC_N3000_AUTH_RESULT 0x404
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/* Doorbell register fields */
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#define DRBL_RSU_REQUEST BIT(0)
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#define DRBL_RSU_PROGRESS GENMASK(7, 4)
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#define DRBL_HOST_STATUS GENMASK(11, 8)
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#define DRBL_RSU_STATUS GENMASK(23, 16)
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#define DRBL_PKVL_EEPROM_LOAD_SEC BIT(24)
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#define DRBL_PKVL1_POLL_EN BIT(25)
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#define DRBL_PKVL2_POLL_EN BIT(26)
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#define DRBL_CONFIG_SEL BIT(28)
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#define DRBL_REBOOT_REQ BIT(29)
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#define DRBL_REBOOT_DISABLED BIT(30)
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/* Progress states */
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#define RSU_PROG_IDLE 0x0
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#define RSU_PROG_PREPARE 0x1
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#define RSU_PROG_READY 0x3
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#define RSU_PROG_AUTHENTICATING 0x4
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#define RSU_PROG_COPYING 0x5
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#define RSU_PROG_UPDATE_CANCEL 0x6
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#define RSU_PROG_PROGRAM_KEY_HASH 0x7
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#define RSU_PROG_RSU_DONE 0x8
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#define RSU_PROG_PKVL_PROM_DONE 0x9
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/* Device and error states */
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#define RSU_STAT_NORMAL 0x0
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#define RSU_STAT_TIMEOUT 0x1
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#define RSU_STAT_AUTH_FAIL 0x2
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#define RSU_STAT_COPY_FAIL 0x3
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#define RSU_STAT_FATAL 0x4
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#define RSU_STAT_PKVL_REJECT 0x5
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#define RSU_STAT_NON_INC 0x6
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#define RSU_STAT_ERASE_FAIL 0x7
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#define RSU_STAT_WEAROUT 0x8
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#define RSU_STAT_NIOS_OK 0x80
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#define RSU_STAT_USER_OK 0x81
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#define RSU_STAT_FACTORY_OK 0x82
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#define RSU_STAT_USER_FAIL 0x83
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#define RSU_STAT_FACTORY_FAIL 0x84
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#define RSU_STAT_NIOS_FLASH_ERR 0x85
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#define RSU_STAT_FPGA_FLASH_ERR 0x86
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#define HOST_STATUS_IDLE 0x0
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#define HOST_STATUS_WRITE_DONE 0x1
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#define HOST_STATUS_ABORT_RSU 0x2
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#define rsu_prog(doorbell) FIELD_GET(DRBL_RSU_PROGRESS, doorbell)
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/* interval 100ms and timeout 5s */
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#define NIOS_HANDSHAKE_INTERVAL_US (100 * 1000)
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#define NIOS_HANDSHAKE_TIMEOUT_US (5 * 1000 * 1000)
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/* RSU PREP Timeout (2 minutes) to erase flash staging area */
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#define RSU_PREP_INTERVAL_MS 100
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#define RSU_PREP_TIMEOUT_MS (2 * 60 * 1000)
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/* RSU Complete Timeout (40 minutes) for full flash update */
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#define RSU_COMPLETE_INTERVAL_MS 1000
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#define RSU_COMPLETE_TIMEOUT_MS (40 * 60 * 1000)
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/* Addresses for security related data in FLASH */
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#define M10BMC_N3000_BMC_REH_ADDR 0x17ffc004
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#define M10BMC_N3000_BMC_PROG_ADDR 0x17ffc000
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#define M10BMC_N3000_BMC_PROG_MAGIC 0x5746
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#define M10BMC_N3000_SR_REH_ADDR 0x17ffd004
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#define M10BMC_N3000_SR_PROG_ADDR 0x17ffd000
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#define M10BMC_N3000_SR_PROG_MAGIC 0x5253
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#define M10BMC_N3000_PR_REH_ADDR 0x17ffe004
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#define M10BMC_N3000_PR_PROG_ADDR 0x17ffe000
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#define M10BMC_N3000_PR_PROG_MAGIC 0x5250
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/* Address of 4KB inverted bit vector containing staging area FLASH count */
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#define M10BMC_N3000_STAGING_FLASH_COUNT 0x17ffb000
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#define M10BMC_N6000_INDIRECT_BASE 0x400
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#define M10BMC_N6000_SYS_BASE 0x0
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#define M10BMC_N6000_SYS_END 0xfff
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#define M10BMC_N6000_DOORBELL 0x1c0
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#define M10BMC_N6000_AUTH_RESULT 0x1c4
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#define AUTH_RESULT_RSU_STATUS GENMASK(23, 16)
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#define M10BMC_N6000_BUILD_VER 0x0
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#define NIOS2_N6000_FW_VERSION 0x4
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#define M10BMC_N6000_MAC_LOW 0x20
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#define M10BMC_N6000_MAC_HIGH (M10BMC_N6000_MAC_LOW + 4)
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/* Addresses for security related data in FLASH */
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#define M10BMC_N6000_BMC_REH_ADDR 0x7ffc004
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#define M10BMC_N6000_BMC_PROG_ADDR 0x7ffc000
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#define M10BMC_N6000_BMC_PROG_MAGIC 0x5746
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#define M10BMC_N6000_SR_REH_ADDR 0x7ffd004
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#define M10BMC_N6000_SR_PROG_ADDR 0x7ffd000
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#define M10BMC_N6000_SR_PROG_MAGIC 0x5253
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#define M10BMC_N6000_PR_REH_ADDR 0x7ffe004
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#define M10BMC_N6000_PR_PROG_ADDR 0x7ffe000
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#define M10BMC_N6000_PR_PROG_MAGIC 0x5250
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#define M10BMC_N6000_STAGING_FLASH_COUNT 0x7ff5000
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#define M10BMC_N6000_FLASH_MUX_CTRL 0x1d0
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#define M10BMC_N6000_FLASH_MUX_SELECTION GENMASK(2, 0)
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#define M10BMC_N6000_FLASH_MUX_IDLE 0
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#define M10BMC_N6000_FLASH_MUX_NIOS 1
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#define M10BMC_N6000_FLASH_MUX_HOST 2
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#define M10BMC_N6000_FLASH_MUX_PFL 4
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#define get_flash_mux(mux) FIELD_GET(M10BMC_N6000_FLASH_MUX_SELECTION, mux)
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#define M10BMC_N6000_FLASH_NIOS_REQUEST BIT(4)
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#define M10BMC_N6000_FLASH_HOST_REQUEST BIT(5)
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#define M10BMC_N6000_FLASH_CTRL 0x40
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#define M10BMC_N6000_FLASH_WR_MODE BIT(0)
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#define M10BMC_N6000_FLASH_RD_MODE BIT(1)
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#define M10BMC_N6000_FLASH_BUSY BIT(2)
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#define M10BMC_N6000_FLASH_FIFO_SPACE GENMASK(13, 4)
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#define M10BMC_N6000_FLASH_READ_COUNT GENMASK(25, 16)
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#define M10BMC_N6000_FLASH_ADDR 0x44
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#define M10BMC_N6000_FLASH_FIFO 0x800
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#define M10BMC_N6000_READ_BLOCK_SIZE 0x800
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#define M10BMC_N6000_FIFO_MAX_BYTES 0x800
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#define M10BMC_N6000_FIFO_WORD_SIZE 4
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#define M10BMC_N6000_FIFO_MAX_WORDS (M10BMC_N6000_FIFO_MAX_BYTES / \
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M10BMC_N6000_FIFO_WORD_SIZE)
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#define M10BMC_FLASH_INT_US 1
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#define M10BMC_FLASH_TIMEOUT_US 10000
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/**
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* struct m10bmc_csr_map - Intel MAX 10 BMC CSR register map
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*/
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struct m10bmc_csr_map {
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unsigned int base;
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unsigned int build_version;
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unsigned int fw_version;
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unsigned int mac_low;
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unsigned int mac_high;
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unsigned int doorbell;
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unsigned int auth_result;
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unsigned int bmc_prog_addr;
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unsigned int bmc_reh_addr;
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unsigned int bmc_magic;
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unsigned int sr_prog_addr;
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unsigned int sr_reh_addr;
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unsigned int sr_magic;
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unsigned int pr_prog_addr;
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unsigned int pr_reh_addr;
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unsigned int pr_magic;
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unsigned int rsu_update_counter;
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};
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/**
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* struct intel_m10bmc_platform_info - Intel MAX 10 BMC platform specific information
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* @cells: MFD cells
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* @n_cells: MFD cells ARRAY_SIZE()
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* @handshake_sys_reg_ranges: array of register ranges for fw handshake regs
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* @handshake_sys_reg_nranges: number of register ranges for fw handshake regs
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* @csr_map: the mappings for register definition of MAX10 BMC
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*/
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struct intel_m10bmc_platform_info {
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struct mfd_cell *cells;
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int n_cells;
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const struct regmap_range *handshake_sys_reg_ranges;
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unsigned int handshake_sys_reg_nranges;
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const struct m10bmc_csr_map *csr_map;
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};
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struct intel_m10bmc;
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/**
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* struct intel_m10bmc_flash_bulk_ops - device specific operations for flash R/W
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* @read: read a block of data from flash
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* @write: write a block of data to flash
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* @lock_write: locks flash access for erase+write
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* @unlock_write: unlock flash access
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*
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* Write must be protected with @lock_write and @unlock_write. While the flash
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* is locked, @read returns -EBUSY.
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*/
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struct intel_m10bmc_flash_bulk_ops {
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int (*read)(struct intel_m10bmc *m10bmc, u8 *buf, u32 addr, u32 size);
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int (*write)(struct intel_m10bmc *m10bmc, const u8 *buf, u32 offset, u32 size);
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int (*lock_write)(struct intel_m10bmc *m10bmc);
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void (*unlock_write)(struct intel_m10bmc *m10bmc);
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};
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enum m10bmc_fw_state {
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M10BMC_FW_STATE_NORMAL,
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M10BMC_FW_STATE_SEC_UPDATE_PREPARE,
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M10BMC_FW_STATE_SEC_UPDATE_WRITE,
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M10BMC_FW_STATE_SEC_UPDATE_PROGRAM,
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};
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/**
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* struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure
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* @dev: this device
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* @regmap: the regmap used to access registers by m10bmc itself
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* @info: the platform information for MAX10 BMC
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* @flash_bulk_ops: optional device specific operations for flash R/W
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* @bmcfw_lock: read/write semaphore to BMC firmware running state
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* @bmcfw_state: BMC firmware running state. Available only when
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* handshake_sys_reg_nranges > 0.
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*/
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struct intel_m10bmc {
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struct device *dev;
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struct regmap *regmap;
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const struct intel_m10bmc_platform_info *info;
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const struct intel_m10bmc_flash_bulk_ops *flash_bulk_ops;
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struct rw_semaphore bmcfw_lock; /* Protects bmcfw_state */
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enum m10bmc_fw_state bmcfw_state;
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};
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/*
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* register access helper functions.
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*
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* m10bmc_raw_read - read m10bmc register per addr
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* m10bmc_sys_read - read m10bmc system register per offset
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* m10bmc_sys_update_bits - update m10bmc system register per offset
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*/
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static inline int
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m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr,
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unsigned int *val)
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{
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int ret;
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ret = regmap_read(m10bmc->regmap, addr, val);
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if (ret)
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dev_err(m10bmc->dev, "fail to read raw reg %x: %d\n",
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addr, ret);
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return ret;
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}
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int m10bmc_sys_read(struct intel_m10bmc *m10bmc, unsigned int offset, unsigned int *val);
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int m10bmc_sys_update_bits(struct intel_m10bmc *m10bmc, unsigned int offset,
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unsigned int msk, unsigned int val);
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/*
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* Track the state of the firmware, as it is not available for register
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* handshakes during secure updates on some MAX 10 cards.
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*/
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void m10bmc_fw_state_set(struct intel_m10bmc *m10bmc, enum m10bmc_fw_state new_state);
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/*
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* MAX10 BMC Core support
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*/
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int m10bmc_dev_init(struct intel_m10bmc *m10bmc, const struct intel_m10bmc_platform_info *info);
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extern const struct attribute_group *m10bmc_dev_groups[];
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#endif /* __MFD_INTEL_M10_BMC_H */
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