519 lines
15 KiB
C
519 lines
15 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_ih.h"
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#include "soc15.h"
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#include "oss/osssys_4_0_offset.h"
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#include "oss/osssys_4_0_sh_mask.h"
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#include "soc15_common.h"
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#include "vega10_ih.h"
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static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
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/**
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* vega10_ih_enable_interrupts - Enable the interrupt ring buffer
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*
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* @adev: amdgpu_device pointer
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*
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* Enable the interrupt ring buffer (VEGA10).
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*/
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static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
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{
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u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
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adev->irq.ih.enabled = true;
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}
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/**
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* vega10_ih_disable_interrupts - Disable the interrupt ring buffer
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*
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* @adev: amdgpu_device pointer
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*
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* Disable the interrupt ring buffer (VEGA10).
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*/
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static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
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{
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u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
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/* set rptr, wptr to 0 */
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
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adev->irq.ih.enabled = false;
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adev->irq.ih.rptr = 0;
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}
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/**
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* vega10_ih_irq_init - init and enable the interrupt ring
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*
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* @adev: amdgpu_device pointer
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*
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* Allocate a ring buffer for the interrupt controller,
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* enable the RLC, disable interrupts, enable the IH
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* ring buffer and enable it (VI).
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* Called at device load and reume.
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* Returns 0 for success, errors for failure.
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*/
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static int vega10_ih_irq_init(struct amdgpu_device *adev)
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{
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int ret = 0;
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int rb_bufsz;
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u32 ih_rb_cntl, ih_doorbell_rtpr;
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u32 tmp;
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u64 wptr_off;
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/* disable irqs */
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vega10_ih_disable_interrupts(adev);
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adev->nbio_funcs->ih_control(adev);
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ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
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/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
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if (adev->irq.ih.use_bus_addr) {
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1);
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} else {
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (adev->irq.ih.gpu_addr >> 40) & 0xff);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4);
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}
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rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
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/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
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if (adev->irq.msi_enabled)
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
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/* set the writeback address whether it's enabled or not */
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if (adev->irq.ih.use_bus_addr)
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wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);
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else
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wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
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/* set rptr, wptr to 0 */
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
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ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR);
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if (adev->irq.ih.use_doorbell) {
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ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
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OFFSET, adev->irq.ih.doorbell_index);
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ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
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ENABLE, 1);
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} else {
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ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
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ENABLE, 0);
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}
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WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
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adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
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adev->irq.ih.doorbell_index);
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tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
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tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
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CLIENT18_IS_STORM_CLIENT, 1);
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WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp);
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tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL);
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tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
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WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp);
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pci_set_master(adev->pdev);
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/* enable interrupts */
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vega10_ih_enable_interrupts(adev);
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return ret;
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}
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/**
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* vega10_ih_irq_disable - disable interrupts
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*
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* @adev: amdgpu_device pointer
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*
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* Disable interrupts on the hw (VEGA10).
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*/
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static void vega10_ih_irq_disable(struct amdgpu_device *adev)
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{
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vega10_ih_disable_interrupts(adev);
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/* Wait and acknowledge irq */
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mdelay(1);
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}
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/**
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* vega10_ih_get_wptr - get the IH ring buffer wptr
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*
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* @adev: amdgpu_device pointer
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*
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* Get the IH ring buffer wptr from either the register
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* or the writeback memory buffer (VEGA10). Also check for
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* ring buffer overflow and deal with it.
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* Returns the value of the wptr.
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*/
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static u32 vega10_ih_get_wptr(struct amdgpu_device *adev)
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{
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u32 wptr, tmp;
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if (adev->irq.ih.use_bus_addr)
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wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
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else
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wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
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if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
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wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
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/* When a ring buffer overflow happen start parsing interrupt
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* from the last not overwritten vector (wptr + 32). Hopefully
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* this should allow us to catchup.
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*/
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tmp = (wptr + 32) & adev->irq.ih.ptr_mask;
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dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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wptr, adev->irq.ih.rptr, tmp);
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adev->irq.ih.rptr = tmp;
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tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp);
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}
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return (wptr & adev->irq.ih.ptr_mask);
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}
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/**
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* vega10_ih_prescreen_iv - prescreen an interrupt vector
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*
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* @adev: amdgpu_device pointer
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*
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* Returns true if the interrupt vector should be further processed.
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*/
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static bool vega10_ih_prescreen_iv(struct amdgpu_device *adev)
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{
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u32 ring_index = adev->irq.ih.rptr >> 2;
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u32 dw0, dw3, dw4, dw5;
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u16 pasid;
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u64 addr, key;
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struct amdgpu_vm *vm;
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int r;
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dw0 = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
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dw3 = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
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dw4 = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]);
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dw5 = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]);
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/* Filter retry page faults, let only the first one pass. If
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* there are too many outstanding faults, ignore them until
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* some faults get cleared.
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*/
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switch (dw0 & 0xff) {
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case SOC15_IH_CLIENTID_VMC:
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case SOC15_IH_CLIENTID_UTCL2:
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break;
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default:
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/* Not a VM fault */
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return true;
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}
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pasid = dw3 & 0xffff;
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/* No PASID, can't identify faulting process */
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if (!pasid)
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return true;
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/* Not a retry fault, check fault credit */
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if (!(dw5 & 0x80)) {
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if (!amdgpu_vm_pasid_fault_credit(adev, pasid))
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goto ignore_iv;
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return true;
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}
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addr = ((u64)(dw5 & 0xf) << 44) | ((u64)dw4 << 12);
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key = AMDGPU_VM_FAULT(pasid, addr);
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r = amdgpu_ih_add_fault(adev, key);
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/* Hash table is full or the fault is already being processed,
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* ignore further page faults
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*/
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if (r != 0)
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goto ignore_iv;
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/* Track retry faults in per-VM fault FIFO. */
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spin_lock(&adev->vm_manager.pasid_lock);
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vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
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if (!vm) {
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/* VM not found, process it normally */
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spin_unlock(&adev->vm_manager.pasid_lock);
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amdgpu_ih_clear_fault(adev, key);
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return true;
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}
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/* No locking required with single writer and single reader */
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r = kfifo_put(&vm->faults, key);
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if (!r) {
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/* FIFO is full. Ignore it until there is space */
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spin_unlock(&adev->vm_manager.pasid_lock);
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amdgpu_ih_clear_fault(adev, key);
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goto ignore_iv;
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}
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spin_unlock(&adev->vm_manager.pasid_lock);
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/* It's the first fault for this address, process it normally */
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return true;
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ignore_iv:
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adev->irq.ih.rptr += 32;
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return false;
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}
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/**
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* vega10_ih_decode_iv - decode an interrupt vector
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*
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* @adev: amdgpu_device pointer
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*
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* Decodes the interrupt vector at the current rptr
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* position and also advance the position.
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*/
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static void vega10_ih_decode_iv(struct amdgpu_device *adev,
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struct amdgpu_iv_entry *entry)
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{
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/* wptr/rptr are in bytes! */
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u32 ring_index = adev->irq.ih.rptr >> 2;
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uint32_t dw[8];
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dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
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dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
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dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
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dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
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dw[4] = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]);
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dw[5] = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]);
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dw[6] = le32_to_cpu(adev->irq.ih.ring[ring_index + 6]);
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dw[7] = le32_to_cpu(adev->irq.ih.ring[ring_index + 7]);
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entry->client_id = dw[0] & 0xff;
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entry->src_id = (dw[0] >> 8) & 0xff;
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entry->ring_id = (dw[0] >> 16) & 0xff;
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entry->vmid = (dw[0] >> 24) & 0xf;
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entry->vmid_src = (dw[0] >> 31);
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entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);
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entry->timestamp_src = dw[2] >> 31;
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entry->pasid = dw[3] & 0xffff;
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entry->pasid_src = dw[3] >> 31;
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entry->src_data[0] = dw[4];
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entry->src_data[1] = dw[5];
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entry->src_data[2] = dw[6];
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entry->src_data[3] = dw[7];
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/* wptr/rptr are in bytes! */
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adev->irq.ih.rptr += 32;
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}
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/**
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* vega10_ih_set_rptr - set the IH ring buffer rptr
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*
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* @adev: amdgpu_device pointer
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*
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* Set the IH ring buffer rptr.
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*/
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static void vega10_ih_set_rptr(struct amdgpu_device *adev)
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{
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if (adev->irq.ih.use_doorbell) {
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/* XXX check if swapping is necessary on BE */
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if (adev->irq.ih.use_bus_addr)
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adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
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else
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adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
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WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
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} else {
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, adev->irq.ih.rptr);
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}
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}
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static int vega10_ih_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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vega10_ih_set_interrupt_funcs(adev);
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return 0;
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}
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static int vega10_ih_sw_init(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = amdgpu_ih_ring_init(adev, 256 * 1024, true);
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if (r)
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return r;
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adev->irq.ih.use_doorbell = true;
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adev->irq.ih.doorbell_index = AMDGPU_DOORBELL64_IH << 1;
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adev->irq.ih.faults = kmalloc(sizeof(*adev->irq.ih.faults), GFP_KERNEL);
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if (!adev->irq.ih.faults)
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return -ENOMEM;
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INIT_CHASH_TABLE(adev->irq.ih.faults->hash,
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AMDGPU_PAGEFAULT_HASH_BITS, 8, 0);
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spin_lock_init(&adev->irq.ih.faults->lock);
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adev->irq.ih.faults->count = 0;
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r = amdgpu_irq_init(adev);
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return r;
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}
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static int vega10_ih_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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amdgpu_irq_fini(adev);
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amdgpu_ih_ring_fini(adev);
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kfree(adev->irq.ih.faults);
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adev->irq.ih.faults = NULL;
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return 0;
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}
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static int vega10_ih_hw_init(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = vega10_ih_irq_init(adev);
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if (r)
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return r;
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return 0;
|
|
}
|
|
|
|
static int vega10_ih_hw_fini(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
vega10_ih_irq_disable(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vega10_ih_suspend(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
return vega10_ih_hw_fini(adev);
|
|
}
|
|
|
|
static int vega10_ih_resume(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
return vega10_ih_hw_init(adev);
|
|
}
|
|
|
|
static bool vega10_ih_is_idle(void *handle)
|
|
{
|
|
/* todo */
|
|
return true;
|
|
}
|
|
|
|
static int vega10_ih_wait_for_idle(void *handle)
|
|
{
|
|
/* todo */
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
static int vega10_ih_soft_reset(void *handle)
|
|
{
|
|
/* todo */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vega10_ih_set_clockgating_state(void *handle,
|
|
enum amd_clockgating_state state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int vega10_ih_set_powergating_state(void *handle,
|
|
enum amd_powergating_state state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
const struct amd_ip_funcs vega10_ih_ip_funcs = {
|
|
.name = "vega10_ih",
|
|
.early_init = vega10_ih_early_init,
|
|
.late_init = NULL,
|
|
.sw_init = vega10_ih_sw_init,
|
|
.sw_fini = vega10_ih_sw_fini,
|
|
.hw_init = vega10_ih_hw_init,
|
|
.hw_fini = vega10_ih_hw_fini,
|
|
.suspend = vega10_ih_suspend,
|
|
.resume = vega10_ih_resume,
|
|
.is_idle = vega10_ih_is_idle,
|
|
.wait_for_idle = vega10_ih_wait_for_idle,
|
|
.soft_reset = vega10_ih_soft_reset,
|
|
.set_clockgating_state = vega10_ih_set_clockgating_state,
|
|
.set_powergating_state = vega10_ih_set_powergating_state,
|
|
};
|
|
|
|
static const struct amdgpu_ih_funcs vega10_ih_funcs = {
|
|
.get_wptr = vega10_ih_get_wptr,
|
|
.prescreen_iv = vega10_ih_prescreen_iv,
|
|
.decode_iv = vega10_ih_decode_iv,
|
|
.set_rptr = vega10_ih_set_rptr
|
|
};
|
|
|
|
static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
|
|
{
|
|
if (adev->irq.ih_funcs == NULL)
|
|
adev->irq.ih_funcs = &vega10_ih_funcs;
|
|
}
|
|
|
|
const struct amdgpu_ip_block_version vega10_ih_ip_block =
|
|
{
|
|
.type = AMD_IP_BLOCK_TYPE_IH,
|
|
.major = 4,
|
|
.minor = 0,
|
|
.rev = 0,
|
|
.funcs = &vega10_ih_ip_funcs,
|
|
};
|