1047 lines
28 KiB
C
1047 lines
28 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for HiSilicon PCIe tune and trace device
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*
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* Copyright (c) 2022 HiSilicon Technologies Co., Ltd.
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* Author: Yicong Yang <yangyicong@hisilicon.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/cpuhotplug.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iommu.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/sysfs.h>
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#include <linux/vmalloc.h>
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#include "hisi_ptt.h"
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/* Dynamic CPU hotplug state used by PTT */
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static enum cpuhp_state hisi_ptt_pmu_online;
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static bool hisi_ptt_wait_tuning_finish(struct hisi_ptt *hisi_ptt)
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{
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u32 val;
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return !readl_poll_timeout(hisi_ptt->iobase + HISI_PTT_TUNING_INT_STAT,
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val, !(val & HISI_PTT_TUNING_INT_STAT_MASK),
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HISI_PTT_WAIT_POLL_INTERVAL_US,
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HISI_PTT_WAIT_TUNE_TIMEOUT_US);
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}
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static ssize_t hisi_ptt_tune_attr_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct hisi_ptt *hisi_ptt = to_hisi_ptt(dev_get_drvdata(dev));
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struct dev_ext_attribute *ext_attr;
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struct hisi_ptt_tune_desc *desc;
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u32 reg;
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u16 val;
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ext_attr = container_of(attr, struct dev_ext_attribute, attr);
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desc = ext_attr->var;
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mutex_lock(&hisi_ptt->tune_lock);
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reg = readl(hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
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reg &= ~(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB);
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reg |= FIELD_PREP(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB,
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desc->event_code);
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writel(reg, hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
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/* Write all 1 to indicates it's the read process */
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writel(~0U, hisi_ptt->iobase + HISI_PTT_TUNING_DATA);
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if (!hisi_ptt_wait_tuning_finish(hisi_ptt)) {
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mutex_unlock(&hisi_ptt->tune_lock);
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return -ETIMEDOUT;
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}
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reg = readl(hisi_ptt->iobase + HISI_PTT_TUNING_DATA);
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reg &= HISI_PTT_TUNING_DATA_VAL_MASK;
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val = FIELD_GET(HISI_PTT_TUNING_DATA_VAL_MASK, reg);
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mutex_unlock(&hisi_ptt->tune_lock);
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return sysfs_emit(buf, "%u\n", val);
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}
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static ssize_t hisi_ptt_tune_attr_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct hisi_ptt *hisi_ptt = to_hisi_ptt(dev_get_drvdata(dev));
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struct dev_ext_attribute *ext_attr;
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struct hisi_ptt_tune_desc *desc;
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u32 reg;
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u16 val;
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ext_attr = container_of(attr, struct dev_ext_attribute, attr);
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desc = ext_attr->var;
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if (kstrtou16(buf, 10, &val))
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return -EINVAL;
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mutex_lock(&hisi_ptt->tune_lock);
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reg = readl(hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
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reg &= ~(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB);
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reg |= FIELD_PREP(HISI_PTT_TUNING_CTRL_CODE | HISI_PTT_TUNING_CTRL_SUB,
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desc->event_code);
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writel(reg, hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
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writel(FIELD_PREP(HISI_PTT_TUNING_DATA_VAL_MASK, val),
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hisi_ptt->iobase + HISI_PTT_TUNING_DATA);
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if (!hisi_ptt_wait_tuning_finish(hisi_ptt)) {
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mutex_unlock(&hisi_ptt->tune_lock);
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return -ETIMEDOUT;
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}
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mutex_unlock(&hisi_ptt->tune_lock);
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return count;
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}
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#define HISI_PTT_TUNE_ATTR(_name, _val, _show, _store) \
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static struct hisi_ptt_tune_desc _name##_desc = { \
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.name = #_name, \
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.event_code = (_val), \
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}; \
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static struct dev_ext_attribute hisi_ptt_##_name##_attr = { \
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.attr = __ATTR(_name, 0600, _show, _store), \
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.var = &_name##_desc, \
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}
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#define HISI_PTT_TUNE_ATTR_COMMON(_name, _val) \
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HISI_PTT_TUNE_ATTR(_name, _val, \
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hisi_ptt_tune_attr_show, \
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hisi_ptt_tune_attr_store)
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/*
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* The value of the tuning event are composed of two parts: main event code
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* in BIT[0,15] and subevent code in BIT[16,23]. For example, qox_tx_cpl is
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* a subevent of 'Tx path QoS control' which for tuning the weight of Tx
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* completion TLPs. See hisi_ptt.rst documentation for more information.
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*/
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#define HISI_PTT_TUNE_QOS_TX_CPL (0x4 | (3 << 16))
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#define HISI_PTT_TUNE_QOS_TX_NP (0x4 | (4 << 16))
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#define HISI_PTT_TUNE_QOS_TX_P (0x4 | (5 << 16))
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#define HISI_PTT_TUNE_RX_ALLOC_BUF_LEVEL (0x5 | (6 << 16))
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#define HISI_PTT_TUNE_TX_ALLOC_BUF_LEVEL (0x5 | (7 << 16))
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HISI_PTT_TUNE_ATTR_COMMON(qos_tx_cpl, HISI_PTT_TUNE_QOS_TX_CPL);
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HISI_PTT_TUNE_ATTR_COMMON(qos_tx_np, HISI_PTT_TUNE_QOS_TX_NP);
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HISI_PTT_TUNE_ATTR_COMMON(qos_tx_p, HISI_PTT_TUNE_QOS_TX_P);
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HISI_PTT_TUNE_ATTR_COMMON(rx_alloc_buf_level, HISI_PTT_TUNE_RX_ALLOC_BUF_LEVEL);
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HISI_PTT_TUNE_ATTR_COMMON(tx_alloc_buf_level, HISI_PTT_TUNE_TX_ALLOC_BUF_LEVEL);
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static struct attribute *hisi_ptt_tune_attrs[] = {
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&hisi_ptt_qos_tx_cpl_attr.attr.attr,
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&hisi_ptt_qos_tx_np_attr.attr.attr,
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&hisi_ptt_qos_tx_p_attr.attr.attr,
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&hisi_ptt_rx_alloc_buf_level_attr.attr.attr,
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&hisi_ptt_tx_alloc_buf_level_attr.attr.attr,
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NULL,
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};
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static struct attribute_group hisi_ptt_tune_group = {
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.name = "tune",
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.attrs = hisi_ptt_tune_attrs,
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};
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static u16 hisi_ptt_get_filter_val(u16 devid, bool is_port)
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{
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if (is_port)
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return BIT(HISI_PCIE_CORE_PORT_ID(devid & 0xff));
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return devid;
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}
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static bool hisi_ptt_wait_trace_hw_idle(struct hisi_ptt *hisi_ptt)
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{
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u32 val;
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return !readl_poll_timeout_atomic(hisi_ptt->iobase + HISI_PTT_TRACE_STS,
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val, val & HISI_PTT_TRACE_IDLE,
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HISI_PTT_WAIT_POLL_INTERVAL_US,
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HISI_PTT_WAIT_TRACE_TIMEOUT_US);
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}
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static void hisi_ptt_wait_dma_reset_done(struct hisi_ptt *hisi_ptt)
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{
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u32 val;
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readl_poll_timeout_atomic(hisi_ptt->iobase + HISI_PTT_TRACE_WR_STS,
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val, !val, HISI_PTT_RESET_POLL_INTERVAL_US,
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HISI_PTT_RESET_TIMEOUT_US);
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}
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static void hisi_ptt_trace_end(struct hisi_ptt *hisi_ptt)
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{
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writel(0, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
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hisi_ptt->trace_ctrl.started = false;
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}
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static int hisi_ptt_trace_start(struct hisi_ptt *hisi_ptt)
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{
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struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl;
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u32 val;
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int i;
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/* Check device idle before start trace */
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if (!hisi_ptt_wait_trace_hw_idle(hisi_ptt)) {
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pci_err(hisi_ptt->pdev, "Failed to start trace, the device is still busy\n");
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return -EBUSY;
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}
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ctrl->started = true;
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/* Reset the DMA before start tracing */
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val = readl(hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
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val |= HISI_PTT_TRACE_CTRL_RST;
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writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
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hisi_ptt_wait_dma_reset_done(hisi_ptt);
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val = readl(hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
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val &= ~HISI_PTT_TRACE_CTRL_RST;
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writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
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/* Reset the index of current buffer */
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hisi_ptt->trace_ctrl.buf_index = 0;
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/* Zero the trace buffers */
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for (i = 0; i < HISI_PTT_TRACE_BUF_CNT; i++)
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memset(ctrl->trace_buf[i].addr, 0, HISI_PTT_TRACE_BUF_SIZE);
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/* Clear the interrupt status */
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writel(HISI_PTT_TRACE_INT_STAT_MASK, hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT);
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writel(0, hisi_ptt->iobase + HISI_PTT_TRACE_INT_MASK);
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/* Set the trace control register */
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val = FIELD_PREP(HISI_PTT_TRACE_CTRL_TYPE_SEL, ctrl->type);
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val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_RXTX_SEL, ctrl->direction);
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val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_DATA_FORMAT, ctrl->format);
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val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_TARGET_SEL, hisi_ptt->trace_ctrl.filter);
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if (!hisi_ptt->trace_ctrl.is_port)
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val |= HISI_PTT_TRACE_CTRL_FILTER_MODE;
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/* Start the Trace */
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val |= HISI_PTT_TRACE_CTRL_EN;
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writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
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return 0;
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}
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static int hisi_ptt_update_aux(struct hisi_ptt *hisi_ptt, int index, bool stop)
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{
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struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl;
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struct perf_output_handle *handle = &ctrl->handle;
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struct perf_event *event = handle->event;
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struct hisi_ptt_pmu_buf *buf;
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size_t size;
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void *addr;
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buf = perf_get_aux(handle);
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if (!buf || !handle->size)
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return -EINVAL;
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addr = ctrl->trace_buf[ctrl->buf_index].addr;
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/*
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* If we're going to stop, read the size of already traced data from
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* HISI_PTT_TRACE_WR_STS. Otherwise we're coming from the interrupt,
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* the data size is always HISI_PTT_TRACE_BUF_SIZE.
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*/
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if (stop) {
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u32 reg;
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reg = readl(hisi_ptt->iobase + HISI_PTT_TRACE_WR_STS);
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size = FIELD_GET(HISI_PTT_TRACE_WR_STS_WRITE, reg);
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} else {
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size = HISI_PTT_TRACE_BUF_SIZE;
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}
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memcpy(buf->base + buf->pos, addr, size);
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buf->pos += size;
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/*
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* Just commit the traced data if we're going to stop. Otherwise if the
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* resident AUX buffer cannot contain the data of next trace buffer,
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* apply a new one.
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*/
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if (stop) {
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perf_aux_output_end(handle, buf->pos);
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} else if (buf->length - buf->pos < HISI_PTT_TRACE_BUF_SIZE) {
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perf_aux_output_end(handle, buf->pos);
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buf = perf_aux_output_begin(handle, event);
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if (!buf)
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return -EINVAL;
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buf->pos = handle->head % buf->length;
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if (buf->length - buf->pos < HISI_PTT_TRACE_BUF_SIZE) {
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perf_aux_output_end(handle, 0);
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return -EINVAL;
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}
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}
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return 0;
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}
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static irqreturn_t hisi_ptt_isr(int irq, void *context)
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{
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struct hisi_ptt *hisi_ptt = context;
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u32 status, buf_idx;
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status = readl(hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT);
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if (!(status & HISI_PTT_TRACE_INT_STAT_MASK))
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return IRQ_NONE;
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buf_idx = ffs(status) - 1;
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/* Clear the interrupt status of buffer @buf_idx */
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writel(status, hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT);
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/*
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* Update the AUX buffer and cache the current buffer index,
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* as we need to know this and save the data when the trace
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* is ended out of the interrupt handler. End the trace
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* if the updating fails.
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*/
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if (hisi_ptt_update_aux(hisi_ptt, buf_idx, false))
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hisi_ptt_trace_end(hisi_ptt);
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else
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hisi_ptt->trace_ctrl.buf_index = (buf_idx + 1) % HISI_PTT_TRACE_BUF_CNT;
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return IRQ_HANDLED;
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}
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static void hisi_ptt_irq_free_vectors(void *pdev)
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{
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pci_free_irq_vectors(pdev);
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}
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static int hisi_ptt_register_irq(struct hisi_ptt *hisi_ptt)
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{
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struct pci_dev *pdev = hisi_ptt->pdev;
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int ret;
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ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
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if (ret < 0) {
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pci_err(pdev, "failed to allocate irq vector, ret = %d\n", ret);
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return ret;
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}
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ret = devm_add_action_or_reset(&pdev->dev, hisi_ptt_irq_free_vectors, pdev);
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if (ret < 0)
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return ret;
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ret = devm_request_threaded_irq(&pdev->dev,
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pci_irq_vector(pdev, HISI_PTT_TRACE_DMA_IRQ),
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NULL, hisi_ptt_isr, 0,
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DRV_NAME, hisi_ptt);
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if (ret) {
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pci_err(pdev, "failed to request irq %d, ret = %d\n",
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pci_irq_vector(pdev, HISI_PTT_TRACE_DMA_IRQ), ret);
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return ret;
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}
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return 0;
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}
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static int hisi_ptt_init_filters(struct pci_dev *pdev, void *data)
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{
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struct hisi_ptt_filter_desc *filter;
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struct hisi_ptt *hisi_ptt = data;
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/*
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* We won't fail the probe if filter allocation failed here. The filters
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* should be partial initialized and users would know which filter fails
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* through the log. Other functions of PTT device are still available.
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*/
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filter = kzalloc(sizeof(*filter), GFP_KERNEL);
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if (!filter) {
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pci_err(hisi_ptt->pdev, "failed to add filter %s\n", pci_name(pdev));
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return -ENOMEM;
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}
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filter->devid = PCI_DEVID(pdev->bus->number, pdev->devfn);
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if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) {
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filter->is_port = true;
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list_add_tail(&filter->list, &hisi_ptt->port_filters);
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/* Update the available port mask */
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hisi_ptt->port_mask |= hisi_ptt_get_filter_val(filter->devid, true);
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} else {
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list_add_tail(&filter->list, &hisi_ptt->req_filters);
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}
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return 0;
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}
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static void hisi_ptt_release_filters(void *data)
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{
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struct hisi_ptt_filter_desc *filter, *tmp;
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struct hisi_ptt *hisi_ptt = data;
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list_for_each_entry_safe(filter, tmp, &hisi_ptt->req_filters, list) {
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list_del(&filter->list);
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kfree(filter);
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}
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list_for_each_entry_safe(filter, tmp, &hisi_ptt->port_filters, list) {
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list_del(&filter->list);
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kfree(filter);
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}
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}
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static int hisi_ptt_config_trace_buf(struct hisi_ptt *hisi_ptt)
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{
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struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl;
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struct device *dev = &hisi_ptt->pdev->dev;
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int i;
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ctrl->trace_buf = devm_kcalloc(dev, HISI_PTT_TRACE_BUF_CNT,
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sizeof(*ctrl->trace_buf), GFP_KERNEL);
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if (!ctrl->trace_buf)
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return -ENOMEM;
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for (i = 0; i < HISI_PTT_TRACE_BUF_CNT; ++i) {
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ctrl->trace_buf[i].addr = dmam_alloc_coherent(dev, HISI_PTT_TRACE_BUF_SIZE,
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&ctrl->trace_buf[i].dma,
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GFP_KERNEL);
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if (!ctrl->trace_buf[i].addr)
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return -ENOMEM;
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}
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/* Configure the trace DMA buffer */
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for (i = 0; i < HISI_PTT_TRACE_BUF_CNT; i++) {
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writel(lower_32_bits(ctrl->trace_buf[i].dma),
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hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_BASE_LO_0 +
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i * HISI_PTT_TRACE_ADDR_STRIDE);
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writel(upper_32_bits(ctrl->trace_buf[i].dma),
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hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_BASE_HI_0 +
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i * HISI_PTT_TRACE_ADDR_STRIDE);
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}
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writel(HISI_PTT_TRACE_BUF_SIZE, hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_SIZE);
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return 0;
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}
|
|
|
|
static int hisi_ptt_init_ctrls(struct hisi_ptt *hisi_ptt)
|
|
{
|
|
struct pci_dev *pdev = hisi_ptt->pdev;
|
|
struct pci_bus *bus;
|
|
int ret;
|
|
u32 reg;
|
|
|
|
INIT_LIST_HEAD(&hisi_ptt->port_filters);
|
|
INIT_LIST_HEAD(&hisi_ptt->req_filters);
|
|
|
|
ret = hisi_ptt_config_trace_buf(hisi_ptt);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* The device range register provides the information about the root
|
|
* ports which the RCiEP can control and trace. The RCiEP and the root
|
|
* ports which it supports are on the same PCIe core, with same domain
|
|
* number but maybe different bus number. The device range register
|
|
* will tell us which root ports we can support, Bit[31:16] indicates
|
|
* the upper BDF numbers of the root port, while Bit[15:0] indicates
|
|
* the lower.
|
|
*/
|
|
reg = readl(hisi_ptt->iobase + HISI_PTT_DEVICE_RANGE);
|
|
hisi_ptt->upper_bdf = FIELD_GET(HISI_PTT_DEVICE_RANGE_UPPER, reg);
|
|
hisi_ptt->lower_bdf = FIELD_GET(HISI_PTT_DEVICE_RANGE_LOWER, reg);
|
|
|
|
bus = pci_find_bus(pci_domain_nr(pdev->bus), PCI_BUS_NUM(hisi_ptt->upper_bdf));
|
|
if (bus)
|
|
pci_walk_bus(bus, hisi_ptt_init_filters, hisi_ptt);
|
|
|
|
ret = devm_add_action_or_reset(&pdev->dev, hisi_ptt_release_filters, hisi_ptt);
|
|
if (ret)
|
|
return ret;
|
|
|
|
hisi_ptt->trace_ctrl.on_cpu = -1;
|
|
return 0;
|
|
}
|
|
|
|
static ssize_t cpumask_show(struct device *dev, struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
struct hisi_ptt *hisi_ptt = to_hisi_ptt(dev_get_drvdata(dev));
|
|
const cpumask_t *cpumask = cpumask_of_node(dev_to_node(&hisi_ptt->pdev->dev));
|
|
|
|
return cpumap_print_to_pagebuf(true, buf, cpumask);
|
|
}
|
|
static DEVICE_ATTR_RO(cpumask);
|
|
|
|
static struct attribute *hisi_ptt_cpumask_attrs[] = {
|
|
&dev_attr_cpumask.attr,
|
|
NULL
|
|
};
|
|
|
|
static const struct attribute_group hisi_ptt_cpumask_attr_group = {
|
|
.attrs = hisi_ptt_cpumask_attrs,
|
|
};
|
|
|
|
/*
|
|
* Bit 19 indicates the filter type, 1 for Root Port filter and 0 for Requester
|
|
* filter. Bit[15:0] indicates the filter value, for Root Port filter it's
|
|
* a bit mask of desired ports and for Requester filter it's the Requester ID
|
|
* of the desired PCIe function. Bit[18:16] is reserved for extension.
|
|
*
|
|
* See hisi_ptt.rst documentation for detailed information.
|
|
*/
|
|
PMU_FORMAT_ATTR(filter, "config:0-19");
|
|
PMU_FORMAT_ATTR(direction, "config:20-23");
|
|
PMU_FORMAT_ATTR(type, "config:24-31");
|
|
PMU_FORMAT_ATTR(format, "config:32-35");
|
|
|
|
static struct attribute *hisi_ptt_pmu_format_attrs[] = {
|
|
&format_attr_filter.attr,
|
|
&format_attr_direction.attr,
|
|
&format_attr_type.attr,
|
|
&format_attr_format.attr,
|
|
NULL
|
|
};
|
|
|
|
static struct attribute_group hisi_ptt_pmu_format_group = {
|
|
.name = "format",
|
|
.attrs = hisi_ptt_pmu_format_attrs,
|
|
};
|
|
|
|
static const struct attribute_group *hisi_ptt_pmu_groups[] = {
|
|
&hisi_ptt_cpumask_attr_group,
|
|
&hisi_ptt_pmu_format_group,
|
|
&hisi_ptt_tune_group,
|
|
NULL
|
|
};
|
|
|
|
static int hisi_ptt_trace_valid_direction(u32 val)
|
|
{
|
|
/*
|
|
* The direction values have different effects according to the data
|
|
* format (specified in the parentheses). TLP set A/B means different
|
|
* set of TLP types. See hisi_ptt.rst documentation for more details.
|
|
*/
|
|
static const u32 hisi_ptt_trace_available_direction[] = {
|
|
0, /* inbound(4DW) or reserved(8DW) */
|
|
1, /* outbound(4DW) */
|
|
2, /* {in, out}bound(4DW) or inbound(8DW), TLP set A */
|
|
3, /* {in, out}bound(4DW) or inbound(8DW), TLP set B */
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(hisi_ptt_trace_available_direction); i++) {
|
|
if (val == hisi_ptt_trace_available_direction[i])
|
|
return 0;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int hisi_ptt_trace_valid_type(u32 val)
|
|
{
|
|
/* Different types can be set simultaneously */
|
|
static const u32 hisi_ptt_trace_available_type[] = {
|
|
1, /* posted_request */
|
|
2, /* non-posted_request */
|
|
4, /* completion */
|
|
};
|
|
int i;
|
|
|
|
if (!val)
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* Walk the available list and clear the valid bits of
|
|
* the config. If there is any resident bit after the
|
|
* walk then the config is invalid.
|
|
*/
|
|
for (i = 0; i < ARRAY_SIZE(hisi_ptt_trace_available_type); i++)
|
|
val &= ~hisi_ptt_trace_available_type[i];
|
|
|
|
if (val)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int hisi_ptt_trace_valid_format(u32 val)
|
|
{
|
|
static const u32 hisi_ptt_trace_availble_format[] = {
|
|
0, /* 4DW */
|
|
1, /* 8DW */
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(hisi_ptt_trace_availble_format); i++) {
|
|
if (val == hisi_ptt_trace_availble_format[i])
|
|
return 0;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int hisi_ptt_trace_valid_filter(struct hisi_ptt *hisi_ptt, u64 config)
|
|
{
|
|
unsigned long val, port_mask = hisi_ptt->port_mask;
|
|
struct hisi_ptt_filter_desc *filter;
|
|
|
|
hisi_ptt->trace_ctrl.is_port = FIELD_GET(HISI_PTT_PMU_FILTER_IS_PORT, config);
|
|
val = FIELD_GET(HISI_PTT_PMU_FILTER_VAL_MASK, config);
|
|
|
|
/*
|
|
* Port filters are defined as bit mask. For port filters, check
|
|
* the bits in the @val are within the range of hisi_ptt->port_mask
|
|
* and whether it's empty or not, otherwise user has specified
|
|
* some unsupported root ports.
|
|
*
|
|
* For Requester ID filters, walk the available filter list to see
|
|
* whether we have one matched.
|
|
*/
|
|
if (!hisi_ptt->trace_ctrl.is_port) {
|
|
list_for_each_entry(filter, &hisi_ptt->req_filters, list) {
|
|
if (val == hisi_ptt_get_filter_val(filter->devid, filter->is_port))
|
|
return 0;
|
|
}
|
|
} else if (bitmap_subset(&val, &port_mask, BITS_PER_LONG)) {
|
|
return 0;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static void hisi_ptt_pmu_init_configs(struct hisi_ptt *hisi_ptt, struct perf_event *event)
|
|
{
|
|
struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl;
|
|
u32 val;
|
|
|
|
val = FIELD_GET(HISI_PTT_PMU_FILTER_VAL_MASK, event->attr.config);
|
|
hisi_ptt->trace_ctrl.filter = val;
|
|
|
|
val = FIELD_GET(HISI_PTT_PMU_DIRECTION_MASK, event->attr.config);
|
|
ctrl->direction = val;
|
|
|
|
val = FIELD_GET(HISI_PTT_PMU_TYPE_MASK, event->attr.config);
|
|
ctrl->type = val;
|
|
|
|
val = FIELD_GET(HISI_PTT_PMU_FORMAT_MASK, event->attr.config);
|
|
ctrl->format = val;
|
|
}
|
|
|
|
static int hisi_ptt_pmu_event_init(struct perf_event *event)
|
|
{
|
|
struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu);
|
|
int ret;
|
|
u32 val;
|
|
|
|
if (event->cpu < 0) {
|
|
dev_dbg(event->pmu->dev, "Per-task mode not supported\n");
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
if (event->attr.type != hisi_ptt->hisi_ptt_pmu.type)
|
|
return -ENOENT;
|
|
|
|
ret = hisi_ptt_trace_valid_filter(hisi_ptt, event->attr.config);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
val = FIELD_GET(HISI_PTT_PMU_DIRECTION_MASK, event->attr.config);
|
|
ret = hisi_ptt_trace_valid_direction(val);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
val = FIELD_GET(HISI_PTT_PMU_TYPE_MASK, event->attr.config);
|
|
ret = hisi_ptt_trace_valid_type(val);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
val = FIELD_GET(HISI_PTT_PMU_FORMAT_MASK, event->attr.config);
|
|
return hisi_ptt_trace_valid_format(val);
|
|
}
|
|
|
|
static void *hisi_ptt_pmu_setup_aux(struct perf_event *event, void **pages,
|
|
int nr_pages, bool overwrite)
|
|
{
|
|
struct hisi_ptt_pmu_buf *buf;
|
|
struct page **pagelist;
|
|
int i;
|
|
|
|
if (overwrite) {
|
|
dev_warn(event->pmu->dev, "Overwrite mode is not supported\n");
|
|
return NULL;
|
|
}
|
|
|
|
/* If the pages size less than buffers, we cannot start trace */
|
|
if (nr_pages < HISI_PTT_TRACE_TOTAL_BUF_SIZE / PAGE_SIZE)
|
|
return NULL;
|
|
|
|
buf = kzalloc(sizeof(*buf), GFP_KERNEL);
|
|
if (!buf)
|
|
return NULL;
|
|
|
|
pagelist = kcalloc(nr_pages, sizeof(*pagelist), GFP_KERNEL);
|
|
if (!pagelist)
|
|
goto err;
|
|
|
|
for (i = 0; i < nr_pages; i++)
|
|
pagelist[i] = virt_to_page(pages[i]);
|
|
|
|
buf->base = vmap(pagelist, nr_pages, VM_MAP, PAGE_KERNEL);
|
|
if (!buf->base) {
|
|
kfree(pagelist);
|
|
goto err;
|
|
}
|
|
|
|
buf->nr_pages = nr_pages;
|
|
buf->length = nr_pages * PAGE_SIZE;
|
|
buf->pos = 0;
|
|
|
|
kfree(pagelist);
|
|
return buf;
|
|
err:
|
|
kfree(buf);
|
|
return NULL;
|
|
}
|
|
|
|
static void hisi_ptt_pmu_free_aux(void *aux)
|
|
{
|
|
struct hisi_ptt_pmu_buf *buf = aux;
|
|
|
|
vunmap(buf->base);
|
|
kfree(buf);
|
|
}
|
|
|
|
static void hisi_ptt_pmu_start(struct perf_event *event, int flags)
|
|
{
|
|
struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu);
|
|
struct perf_output_handle *handle = &hisi_ptt->trace_ctrl.handle;
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
struct device *dev = event->pmu->dev;
|
|
struct hisi_ptt_pmu_buf *buf;
|
|
int cpu = event->cpu;
|
|
int ret;
|
|
|
|
hwc->state = 0;
|
|
|
|
/* Serialize the perf process if user specified several CPUs */
|
|
spin_lock(&hisi_ptt->pmu_lock);
|
|
if (hisi_ptt->trace_ctrl.started) {
|
|
dev_dbg(dev, "trace has already started\n");
|
|
goto stop;
|
|
}
|
|
|
|
/*
|
|
* Handle the interrupt on the same cpu which starts the trace to avoid
|
|
* context mismatch. Otherwise we'll trigger the WARN from the perf
|
|
* core in event_function_local(). If CPU passed is offline we'll fail
|
|
* here, just log it since we can do nothing here.
|
|
*/
|
|
ret = irq_set_affinity(pci_irq_vector(hisi_ptt->pdev, HISI_PTT_TRACE_DMA_IRQ),
|
|
cpumask_of(cpu));
|
|
if (ret)
|
|
dev_warn(dev, "failed to set the affinity of trace interrupt\n");
|
|
|
|
hisi_ptt->trace_ctrl.on_cpu = cpu;
|
|
|
|
buf = perf_aux_output_begin(handle, event);
|
|
if (!buf) {
|
|
dev_dbg(dev, "aux output begin failed\n");
|
|
goto stop;
|
|
}
|
|
|
|
buf->pos = handle->head % buf->length;
|
|
|
|
hisi_ptt_pmu_init_configs(hisi_ptt, event);
|
|
|
|
ret = hisi_ptt_trace_start(hisi_ptt);
|
|
if (ret) {
|
|
dev_dbg(dev, "trace start failed, ret = %d\n", ret);
|
|
perf_aux_output_end(handle, 0);
|
|
goto stop;
|
|
}
|
|
|
|
spin_unlock(&hisi_ptt->pmu_lock);
|
|
return;
|
|
stop:
|
|
event->hw.state |= PERF_HES_STOPPED;
|
|
spin_unlock(&hisi_ptt->pmu_lock);
|
|
}
|
|
|
|
static void hisi_ptt_pmu_stop(struct perf_event *event, int flags)
|
|
{
|
|
struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu);
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
if (hwc->state & PERF_HES_STOPPED)
|
|
return;
|
|
|
|
spin_lock(&hisi_ptt->pmu_lock);
|
|
if (hisi_ptt->trace_ctrl.started) {
|
|
hisi_ptt_trace_end(hisi_ptt);
|
|
|
|
if (!hisi_ptt_wait_trace_hw_idle(hisi_ptt))
|
|
dev_warn(event->pmu->dev, "Device is still busy\n");
|
|
|
|
hisi_ptt_update_aux(hisi_ptt, hisi_ptt->trace_ctrl.buf_index, true);
|
|
}
|
|
spin_unlock(&hisi_ptt->pmu_lock);
|
|
|
|
hwc->state |= PERF_HES_STOPPED;
|
|
perf_event_update_userpage(event);
|
|
hwc->state |= PERF_HES_UPTODATE;
|
|
}
|
|
|
|
static int hisi_ptt_pmu_add(struct perf_event *event, int flags)
|
|
{
|
|
struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu);
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
int cpu = event->cpu;
|
|
|
|
/* Only allow the cpus on the device's node to add the event */
|
|
if (!cpumask_test_cpu(cpu, cpumask_of_node(dev_to_node(&hisi_ptt->pdev->dev))))
|
|
return 0;
|
|
|
|
hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
|
|
|
|
if (flags & PERF_EF_START) {
|
|
hisi_ptt_pmu_start(event, PERF_EF_RELOAD);
|
|
if (hwc->state & PERF_HES_STOPPED)
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void hisi_ptt_pmu_del(struct perf_event *event, int flags)
|
|
{
|
|
hisi_ptt_pmu_stop(event, PERF_EF_UPDATE);
|
|
}
|
|
|
|
static void hisi_ptt_remove_cpuhp_instance(void *hotplug_node)
|
|
{
|
|
cpuhp_state_remove_instance_nocalls(hisi_ptt_pmu_online, hotplug_node);
|
|
}
|
|
|
|
static void hisi_ptt_unregister_pmu(void *pmu)
|
|
{
|
|
perf_pmu_unregister(pmu);
|
|
}
|
|
|
|
static int hisi_ptt_register_pmu(struct hisi_ptt *hisi_ptt)
|
|
{
|
|
u16 core_id, sicl_id;
|
|
char *pmu_name;
|
|
u32 reg;
|
|
int ret;
|
|
|
|
ret = cpuhp_state_add_instance_nocalls(hisi_ptt_pmu_online,
|
|
&hisi_ptt->hotplug_node);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = devm_add_action_or_reset(&hisi_ptt->pdev->dev,
|
|
hisi_ptt_remove_cpuhp_instance,
|
|
&hisi_ptt->hotplug_node);
|
|
if (ret)
|
|
return ret;
|
|
|
|
mutex_init(&hisi_ptt->tune_lock);
|
|
spin_lock_init(&hisi_ptt->pmu_lock);
|
|
|
|
hisi_ptt->hisi_ptt_pmu = (struct pmu) {
|
|
.module = THIS_MODULE,
|
|
.capabilities = PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE,
|
|
.task_ctx_nr = perf_sw_context,
|
|
.attr_groups = hisi_ptt_pmu_groups,
|
|
.event_init = hisi_ptt_pmu_event_init,
|
|
.setup_aux = hisi_ptt_pmu_setup_aux,
|
|
.free_aux = hisi_ptt_pmu_free_aux,
|
|
.start = hisi_ptt_pmu_start,
|
|
.stop = hisi_ptt_pmu_stop,
|
|
.add = hisi_ptt_pmu_add,
|
|
.del = hisi_ptt_pmu_del,
|
|
};
|
|
|
|
reg = readl(hisi_ptt->iobase + HISI_PTT_LOCATION);
|
|
core_id = FIELD_GET(HISI_PTT_CORE_ID, reg);
|
|
sicl_id = FIELD_GET(HISI_PTT_SICL_ID, reg);
|
|
|
|
pmu_name = devm_kasprintf(&hisi_ptt->pdev->dev, GFP_KERNEL, "hisi_ptt%u_%u",
|
|
sicl_id, core_id);
|
|
if (!pmu_name)
|
|
return -ENOMEM;
|
|
|
|
ret = perf_pmu_register(&hisi_ptt->hisi_ptt_pmu, pmu_name, -1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return devm_add_action_or_reset(&hisi_ptt->pdev->dev,
|
|
hisi_ptt_unregister_pmu,
|
|
&hisi_ptt->hisi_ptt_pmu);
|
|
}
|
|
|
|
/*
|
|
* The DMA of PTT trace can only use direct mappings due to some
|
|
* hardware restriction. Check whether there is no IOMMU or the
|
|
* policy of the IOMMU domain is passthrough, otherwise the trace
|
|
* cannot work.
|
|
*
|
|
* The PTT device is supposed to behind an ARM SMMUv3, which
|
|
* should have passthrough the device by a quirk.
|
|
*/
|
|
static int hisi_ptt_check_iommu_mapping(struct pci_dev *pdev)
|
|
{
|
|
struct iommu_domain *iommu_domain;
|
|
|
|
iommu_domain = iommu_get_domain_for_dev(&pdev->dev);
|
|
if (!iommu_domain || iommu_domain->type == IOMMU_DOMAIN_IDENTITY)
|
|
return 0;
|
|
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
static int hisi_ptt_probe(struct pci_dev *pdev,
|
|
const struct pci_device_id *id)
|
|
{
|
|
struct hisi_ptt *hisi_ptt;
|
|
int ret;
|
|
|
|
ret = hisi_ptt_check_iommu_mapping(pdev);
|
|
if (ret) {
|
|
pci_err(pdev, "requires direct DMA mappings\n");
|
|
return ret;
|
|
}
|
|
|
|
hisi_ptt = devm_kzalloc(&pdev->dev, sizeof(*hisi_ptt), GFP_KERNEL);
|
|
if (!hisi_ptt)
|
|
return -ENOMEM;
|
|
|
|
hisi_ptt->pdev = pdev;
|
|
pci_set_drvdata(pdev, hisi_ptt);
|
|
|
|
ret = pcim_enable_device(pdev);
|
|
if (ret) {
|
|
pci_err(pdev, "failed to enable device, ret = %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = pcim_iomap_regions(pdev, BIT(2), DRV_NAME);
|
|
if (ret) {
|
|
pci_err(pdev, "failed to remap io memory, ret = %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
hisi_ptt->iobase = pcim_iomap_table(pdev)[2];
|
|
|
|
ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
|
|
if (ret) {
|
|
pci_err(pdev, "failed to set 64 bit dma mask, ret = %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
pci_set_master(pdev);
|
|
|
|
ret = hisi_ptt_register_irq(hisi_ptt);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = hisi_ptt_init_ctrls(hisi_ptt);
|
|
if (ret) {
|
|
pci_err(pdev, "failed to init controls, ret = %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = hisi_ptt_register_pmu(hisi_ptt);
|
|
if (ret) {
|
|
pci_err(pdev, "failed to register PMU device, ret = %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pci_device_id hisi_ptt_id_tbl[] = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, 0xa12e) },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, hisi_ptt_id_tbl);
|
|
|
|
static struct pci_driver hisi_ptt_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = hisi_ptt_id_tbl,
|
|
.probe = hisi_ptt_probe,
|
|
};
|
|
|
|
static int hisi_ptt_cpu_teardown(unsigned int cpu, struct hlist_node *node)
|
|
{
|
|
struct hisi_ptt *hisi_ptt;
|
|
struct device *dev;
|
|
int target, src;
|
|
|
|
hisi_ptt = hlist_entry_safe(node, struct hisi_ptt, hotplug_node);
|
|
src = hisi_ptt->trace_ctrl.on_cpu;
|
|
dev = hisi_ptt->hisi_ptt_pmu.dev;
|
|
|
|
if (!hisi_ptt->trace_ctrl.started || src != cpu)
|
|
return 0;
|
|
|
|
target = cpumask_any_but(cpumask_of_node(dev_to_node(&hisi_ptt->pdev->dev)), cpu);
|
|
if (target >= nr_cpu_ids) {
|
|
dev_err(dev, "no available cpu for perf context migration\n");
|
|
return 0;
|
|
}
|
|
|
|
perf_pmu_migrate_context(&hisi_ptt->hisi_ptt_pmu, src, target);
|
|
|
|
/*
|
|
* Also make sure the interrupt bind to the migrated CPU as well. Warn
|
|
* the user on failure here.
|
|
*/
|
|
if (irq_set_affinity(pci_irq_vector(hisi_ptt->pdev, HISI_PTT_TRACE_DMA_IRQ),
|
|
cpumask_of(target)))
|
|
dev_warn(dev, "failed to set the affinity of trace interrupt\n");
|
|
|
|
hisi_ptt->trace_ctrl.on_cpu = target;
|
|
return 0;
|
|
}
|
|
|
|
static int __init hisi_ptt_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRV_NAME, NULL,
|
|
hisi_ptt_cpu_teardown);
|
|
if (ret < 0)
|
|
return ret;
|
|
hisi_ptt_pmu_online = ret;
|
|
|
|
ret = pci_register_driver(&hisi_ptt_driver);
|
|
if (ret)
|
|
cpuhp_remove_multi_state(hisi_ptt_pmu_online);
|
|
|
|
return ret;
|
|
}
|
|
module_init(hisi_ptt_init);
|
|
|
|
static void __exit hisi_ptt_exit(void)
|
|
{
|
|
pci_unregister_driver(&hisi_ptt_driver);
|
|
cpuhp_remove_multi_state(hisi_ptt_pmu_online);
|
|
}
|
|
module_exit(hisi_ptt_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Yicong Yang <yangyicong@hisilicon.com>");
|
|
MODULE_DESCRIPTION("Driver for HiSilicon PCIe tune and trace device");
|