224 lines
6.7 KiB
ArmAsm
224 lines
6.7 KiB
ArmAsm
/*
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* Copyright (C) 2010,2011 Google, Inc.
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* Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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* Erik Gilling <konkers@google.com>
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* Doug Anderson <dianders@chromium.org>
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* Stephen Warren <swarren@nvidia.com>
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*
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* Portions based on mach-omap2's debug-macro.S
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* Copyright (C) 1994-1999 Russell King
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/serial_reg.h>
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#define UART_SHIFT 2
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/* Physical addresses */
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#define TEGRA_CLK_RESET_BASE 0x60006000
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#define TEGRA_APB_MISC_BASE 0x70000000
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#define TEGRA_UARTA_BASE 0x70006000
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#define TEGRA_UARTB_BASE 0x70006040
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#define TEGRA_UARTC_BASE 0x70006200
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#define TEGRA_UARTD_BASE 0x70006300
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#define TEGRA_UARTE_BASE 0x70006400
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#define TEGRA_PMC_BASE 0x7000e400
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#define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
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#define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
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#define TEGRA_CLK_RST_DEVICES_U (TEGRA_CLK_RESET_BASE + 0x0c)
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#define TEGRA_CLK_OUT_ENB_L (TEGRA_CLK_RESET_BASE + 0x10)
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#define TEGRA_CLK_OUT_ENB_H (TEGRA_CLK_RESET_BASE + 0x14)
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#define TEGRA_CLK_OUT_ENB_U (TEGRA_CLK_RESET_BASE + 0x18)
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#define TEGRA_PMC_SCRATCH20 (TEGRA_PMC_BASE + 0xa0)
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#define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804)
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/*
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* Must be 1MB-aligned since a 1MB mapping is used early on.
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* Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
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*/
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#define UART_VIRTUAL_BASE 0xfe100000
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#define checkuart(rp, rv, lhu, bit, uart) \
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/* Load address of CLK_RST register */ \
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movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \
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movt rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \
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/* Load value from CLK_RST register */ \
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ldr rp, [rp, #0] ; \
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/* Test UART's reset bit */ \
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tst rp, #(1 << bit) ; \
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/* If set, can't use UART; jump to save no UART */ \
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bne 90f ; \
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/* Load address of CLK_OUT_ENB register */ \
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movw rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \
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movt rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \
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/* Load value from CLK_OUT_ENB register */ \
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ldr rp, [rp, #0] ; \
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/* Test UART's clock enable bit */ \
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tst rp, #(1 << bit) ; \
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/* If clear, can't use UART; jump to save no UART */ \
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beq 90f ; \
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/* Passed all tests, load address of UART registers */ \
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movw rp, #TEGRA_UART##uart##_BASE & 0xffff ; \
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movt rp, #TEGRA_UART##uart##_BASE >> 16 ; \
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/* Jump to save UART address */ \
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b 91f
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.macro addruart, rp, rv, tmp
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adr \rp, 99f @ actual addr of 99f
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ldr \rv, [\rp] @ linked addr is stored there
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sub \rv, \rv, \rp @ offset between the two
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ldr \rp, [\rp, #4] @ linked tegra_uart_config
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sub \tmp, \rp, \rv @ actual tegra_uart_config
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ldr \rp, [\tmp] @ Load tegra_uart_config
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cmp \rp, #1 @ needs initialization?
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bne 100f @ no; go load the addresses
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mov \rv, #0 @ yes; record init is done
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str \rv, [\tmp]
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#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
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/* Check ODMDATA */
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10: movw \rp, #TEGRA_PMC_SCRATCH20 & 0xffff
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movt \rp, #TEGRA_PMC_SCRATCH20 >> 16
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ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
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ubfx \rv, \rp, #18, #2 @ 19:18 are console type
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cmp \rv, #2 @ 2 and 3 mean DCC, UART
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beq 11f @ some boards swap the meaning
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cmp \rv, #3 @ so accept either
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bne 90f
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11: ubfx \rv, \rp, #15, #3 @ 17:15 are UART ID
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cmp \rv, #0 @ UART 0?
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beq 20f
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cmp \rv, #1 @ UART 1?
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beq 21f
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cmp \rv, #2 @ UART 2?
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beq 22f
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cmp \rv, #3 @ UART 3?
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beq 23f
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cmp \rv, #4 @ UART 4?
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beq 24f
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b 90f @ invalid
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#endif
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#if defined(CONFIG_TEGRA_DEBUG_UARTA) || \
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defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
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/* Check UART A validity */
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20: checkuart(\rp, \rv, L, 6, A)
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#endif
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#if defined(CONFIG_TEGRA_DEBUG_UARTB) || \
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defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
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/* Check UART B validity */
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21: checkuart(\rp, \rv, L, 7, B)
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#endif
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#if defined(CONFIG_TEGRA_DEBUG_UARTC) || \
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defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
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/* Check UART C validity */
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22: checkuart(\rp, \rv, H, 23, C)
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#endif
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#if defined(CONFIG_TEGRA_DEBUG_UARTD) || \
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defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
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/* Check UART D validity */
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23: checkuart(\rp, \rv, U, 1, D)
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#endif
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#if defined(CONFIG_TEGRA_DEBUG_UARTE) || \
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defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
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/* Check UART E validity */
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24:
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checkuart(\rp, \rv, U, 2, E)
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#endif
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/* No valid UART found */
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90: mov \rp, #0
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/* fall through */
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/* Record whichever UART we chose */
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91: str \rp, [\tmp, #4] @ Store in tegra_uart_phys
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cmp \rp, #0 @ Valid UART address?
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bne 92f @ Yes, go process it
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str \rp, [\tmp, #8] @ Store 0 in tegra_uart_virt
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b 100f @ Done
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92: and \rv, \rp, #0xffffff @ offset within 1MB section
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add \rv, \rv, #UART_VIRTUAL_BASE
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str \rv, [\tmp, #8] @ Store in tegra_uart_virt
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movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
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movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
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ldr \rv, [\rv, #0] @ Load HIDREV
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ubfx \rv, \rv, #8, #8 @ 15:8 are SoC version
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cmp \rv, #0x20 @ Tegra20?
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moveq \rv, #0x75 @ Tegra20 divisor
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movne \rv, #0xdd @ Tegra30 divisor
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str \rv, [\tmp, #12] @ Save divisor to scratch
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/* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
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mov \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
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str \rv, [\rp, #UART_LCR << UART_SHIFT]
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/* uart[UART_DLL] = div & 0xff; */
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ldr \rv, [\tmp, #12]
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and \rv, \rv, #0xff
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str \rv, [\rp, #UART_DLL << UART_SHIFT]
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/* uart[UART_DLM] = div >> 8; */
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ldr \rv, [\tmp, #12]
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lsr \rv, \rv, #8
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str \rv, [\rp, #UART_DLM << UART_SHIFT]
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/* uart[UART_LCR] = UART_LCR_WLEN8; */
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mov \rv, #UART_LCR_WLEN8
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str \rv, [\rp, #UART_LCR << UART_SHIFT]
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b 100f
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.align
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99: .word .
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.word tegra_uart_config
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.ltorg
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/* Load previously selected UART address */
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100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
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ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
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.endm
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/*
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* Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
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* check to make sure that the UART address is actually valid.
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*/
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.macro senduart, rd, rx
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cmp \rx, #0
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strneb \rd, [\rx, #UART_TX << UART_SHIFT]
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1001:
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.endm
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.macro busyuart, rd, rx
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cmp \rx, #0
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beq 1002f
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1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
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and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
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teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
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bne 1001b
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1002:
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.endm
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.macro waituart, rd, rx
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#ifdef FLOW_CONTROL
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cmp \rx, #0
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beq 1002f
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1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
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tst \rd, #UART_MSR_CTS
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beq 1001b
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1002:
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#endif
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.endm
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