131 lines
3.4 KiB
C
131 lines
3.4 KiB
C
#ifndef ASM_X86__SYNC_BITOPS_H
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#define ASM_X86__SYNC_BITOPS_H
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/*
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* Copyright 1992, Linus Torvalds.
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*/
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/*
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* These have to be done with inline assembly: that way the bit-setting
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* is guaranteed to be atomic. All bit operations return 0 if the bit
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* was cleared before the operation and != 0 if it was not.
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*
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* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
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*/
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#define ADDR (*(volatile long *)addr)
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/**
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* sync_set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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*
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void sync_set_bit(int nr, volatile unsigned long *addr)
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{
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asm volatile("lock; btsl %1,%0"
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: "+m" (ADDR)
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: "Ir" (nr)
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: "memory");
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}
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/**
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* sync_clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* sync_clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*/
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static inline void sync_clear_bit(int nr, volatile unsigned long *addr)
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{
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asm volatile("lock; btrl %1,%0"
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: "+m" (ADDR)
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: "Ir" (nr)
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: "memory");
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}
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/**
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* sync_change_bit - Toggle a bit in memory
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* @nr: Bit to change
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* @addr: Address to start counting from
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*
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* sync_change_bit() is atomic and may not be reordered.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void sync_change_bit(int nr, volatile unsigned long *addr)
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{
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asm volatile("lock; btcl %1,%0"
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: "+m" (ADDR)
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: "Ir" (nr)
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: "memory");
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}
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/**
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* sync_test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int sync_test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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int oldbit;
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asm volatile("lock; btsl %2,%1\n\tsbbl %0,%0"
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: "=r" (oldbit), "+m" (ADDR)
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: "Ir" (nr) : "memory");
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return oldbit;
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}
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/**
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* sync_test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int sync_test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
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int oldbit;
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asm volatile("lock; btrl %2,%1\n\tsbbl %0,%0"
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: "=r" (oldbit), "+m" (ADDR)
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: "Ir" (nr) : "memory");
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return oldbit;
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}
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/**
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* sync_test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to change
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int sync_test_and_change_bit(int nr, volatile unsigned long *addr)
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{
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int oldbit;
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asm volatile("lock; btcl %2,%1\n\tsbbl %0,%0"
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: "=r" (oldbit), "+m" (ADDR)
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: "Ir" (nr) : "memory");
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return oldbit;
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}
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#define sync_test_bit(nr, addr) test_bit(nr, addr)
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#undef ADDR
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#endif /* ASM_X86__SYNC_BITOPS_H */
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