275 lines
7.1 KiB
C
275 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2017 Cadence
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// Cadence PCIe controller driver.
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// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
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#include <linux/kernel.h>
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#include "pcie-cadence.h"
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void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie)
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{
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u32 delay = 0x3;
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u32 ltssm_control_cap;
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/*
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* Set the LTSSM Detect Quiet state min. delay to 2ms.
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*/
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ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP);
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ltssm_control_cap = ((ltssm_control_cap &
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~CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) |
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CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay));
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cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap);
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}
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void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
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u32 r, bool is_io,
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u64 cpu_addr, u64 pci_addr, size_t size)
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{
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/*
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* roundup_pow_of_two() returns an unsigned long, which is not suited
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* for 64bit values.
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*/
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u64 sz = 1ULL << fls64(size - 1);
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int nbits = ilog2(sz);
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u32 addr0, addr1, desc0, desc1;
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if (nbits < 8)
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nbits = 8;
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/* Set the PCI address */
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addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) |
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(lower_32_bits(pci_addr) & GENMASK(31, 8));
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addr1 = upper_32_bits(pci_addr);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1);
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/* Set the PCIe header descriptor */
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if (is_io)
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desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO;
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else
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desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM;
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desc1 = 0;
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/*
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* Whatever Bit [23] is set or not inside DESC0 register of the outbound
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* PCIe descriptor, the PCI function number must be set into
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* Bits [26:24] of DESC0 anyway.
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*
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* In Root Complex mode, the function number is always 0 but in Endpoint
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* mode, the PCIe controller may support more than one function. This
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* function number needs to be set properly into the outbound PCIe
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* descriptor.
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*
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* Besides, setting Bit [23] is mandatory when in Root Complex mode:
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* then the driver must provide the bus, resp. device, number in
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* Bits [7:0] of DESC1, resp. Bits[31:27] of DESC0. Like the function
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* number, the device number is always 0 in Root Complex mode.
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*
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* However when in Endpoint mode, we can clear Bit [23] of DESC0, hence
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* the PCIe controller will use the captured values for the bus and
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* device numbers.
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*/
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if (pcie->is_rc) {
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/* The device and function numbers are always 0. */
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desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
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CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
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desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(busnr);
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} else {
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/*
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* Use captured values for bus and device numbers but still
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* need to set the function number.
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*/
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desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(fn);
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}
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), desc0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
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/* Set the CPU address */
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if (pcie->ops->cpu_addr_fixup)
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cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
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addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) |
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(lower_32_bits(cpu_addr) & GENMASK(31, 8));
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addr1 = upper_32_bits(cpu_addr);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);
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}
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void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
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u8 busnr, u8 fn,
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u32 r, u64 cpu_addr)
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{
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u32 addr0, addr1, desc0, desc1;
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desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG;
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desc1 = 0;
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/* See cdns_pcie_set_outbound_region() comments above. */
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if (pcie->is_rc) {
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desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
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CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
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desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(busnr);
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} else {
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desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(fn);
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}
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/* Set the CPU address */
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if (pcie->ops->cpu_addr_fixup)
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cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
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addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) |
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(lower_32_bits(cpu_addr) & GENMASK(31, 8));
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addr1 = upper_32_bits(cpu_addr);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), 0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), 0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), desc0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);
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}
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void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r)
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{
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), 0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), 0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), 0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), 0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), 0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), 0);
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}
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void cdns_pcie_disable_phy(struct cdns_pcie *pcie)
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{
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int i = pcie->phy_count;
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while (i--) {
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phy_power_off(pcie->phy[i]);
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phy_exit(pcie->phy[i]);
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}
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}
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int cdns_pcie_enable_phy(struct cdns_pcie *pcie)
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{
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int ret;
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int i;
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for (i = 0; i < pcie->phy_count; i++) {
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ret = phy_init(pcie->phy[i]);
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if (ret < 0)
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goto err_phy;
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ret = phy_power_on(pcie->phy[i]);
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if (ret < 0) {
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phy_exit(pcie->phy[i]);
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goto err_phy;
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}
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}
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return 0;
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err_phy:
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while (--i >= 0) {
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phy_power_off(pcie->phy[i]);
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phy_exit(pcie->phy[i]);
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}
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return ret;
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}
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int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
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{
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struct device_node *np = dev->of_node;
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int phy_count;
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struct phy **phy;
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struct device_link **link;
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int i;
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int ret;
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const char *name;
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phy_count = of_property_count_strings(np, "phy-names");
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if (phy_count < 1) {
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dev_err(dev, "no phy-names. PHY will not be initialized\n");
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pcie->phy_count = 0;
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return 0;
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}
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phy = devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL);
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if (!phy)
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return -ENOMEM;
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link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
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if (!link)
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return -ENOMEM;
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for (i = 0; i < phy_count; i++) {
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of_property_read_string_index(np, "phy-names", i, &name);
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phy[i] = devm_phy_get(dev, name);
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if (IS_ERR(phy[i])) {
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ret = PTR_ERR(phy[i]);
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goto err_phy;
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}
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link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
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if (!link[i]) {
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devm_phy_put(dev, phy[i]);
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ret = -EINVAL;
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goto err_phy;
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}
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}
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pcie->phy_count = phy_count;
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pcie->phy = phy;
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pcie->link = link;
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ret = cdns_pcie_enable_phy(pcie);
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if (ret)
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goto err_phy;
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return 0;
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err_phy:
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while (--i >= 0) {
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device_link_del(link[i]);
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devm_phy_put(dev, phy[i]);
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}
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return ret;
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}
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#ifdef CONFIG_PM_SLEEP
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static int cdns_pcie_suspend_noirq(struct device *dev)
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{
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struct cdns_pcie *pcie = dev_get_drvdata(dev);
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cdns_pcie_disable_phy(pcie);
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return 0;
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}
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static int cdns_pcie_resume_noirq(struct device *dev)
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{
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struct cdns_pcie *pcie = dev_get_drvdata(dev);
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int ret;
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ret = cdns_pcie_enable_phy(pcie);
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if (ret) {
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dev_err(dev, "failed to enable phy\n");
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return ret;
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}
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return 0;
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}
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#endif
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const struct dev_pm_ops cdns_pcie_pm_ops = {
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq,
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cdns_pcie_resume_noirq)
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};
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