641 lines
16 KiB
C
641 lines
16 KiB
C
/*
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* Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers.
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*
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* This driver is heavily based upon:
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*
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* linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
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*
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* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
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* Portions Copyright (C) 2001 Sun Microsystems, Inc.
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* Portions Copyright (C) 2003 Red Hat Inc
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* Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
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*
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*
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* TODO
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* Work out best PLL policy
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_hpt3x2n"
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#define DRV_VERSION "0.3.14"
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enum {
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HPT_PCI_FAST = (1 << 31),
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PCI66 = (1 << 1),
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USE_DPLL = (1 << 0)
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};
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struct hpt_clock {
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u8 xfer_speed;
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u32 timing;
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};
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struct hpt_chip {
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const char *name;
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struct hpt_clock *clocks[3];
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};
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/* key for bus clock timings
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* bit
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* 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
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* cycles = value + 1
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* 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
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* cycles = value + 1
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* 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
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* register access.
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* 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
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* register access.
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* 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
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* 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
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* 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
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* 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
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* register access.
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* 28 UDMA enable.
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* 29 DMA enable.
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* 30 PIO_MST enable. If set, the chip is in bus master mode during
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* PIO xfer.
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* 31 FIFO enable. Only for PIO.
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*/
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/* 66MHz DPLL clocks */
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static struct hpt_clock hpt3x2n_clocks[] = {
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{ XFER_UDMA_7, 0x1c869c62 },
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{ XFER_UDMA_6, 0x1c869c62 },
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{ XFER_UDMA_5, 0x1c8a9c62 },
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{ XFER_UDMA_4, 0x1c8a9c62 },
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{ XFER_UDMA_3, 0x1c8e9c62 },
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{ XFER_UDMA_2, 0x1c929c62 },
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{ XFER_UDMA_1, 0x1c9a9c62 },
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{ XFER_UDMA_0, 0x1c829c62 },
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{ XFER_MW_DMA_2, 0x2c829c62 },
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{ XFER_MW_DMA_1, 0x2c829c66 },
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{ XFER_MW_DMA_0, 0x2c829d2e },
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{ XFER_PIO_4, 0x0c829c62 },
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{ XFER_PIO_3, 0x0c829c84 },
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{ XFER_PIO_2, 0x0c829ca6 },
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{ XFER_PIO_1, 0x0d029d26 },
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{ XFER_PIO_0, 0x0d029d5e },
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};
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/**
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* hpt3x2n_find_mode - reset the hpt3x2n bus
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* @ap: ATA port
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* @speed: transfer mode
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*
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* Return the 32bit register programming information for this channel
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* that matches the speed provided. For the moment the clocks table
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* is hard coded but easy to change. This will be needed if we use
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* different DPLLs
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*/
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static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
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{
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struct hpt_clock *clocks = hpt3x2n_clocks;
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while (clocks->xfer_speed) {
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if (clocks->xfer_speed == speed)
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return clocks->timing;
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clocks++;
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}
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BUG();
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return 0xffffffffU; /* silence compiler warning */
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}
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/**
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* hpt372n_filter - mode selection filter
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* @adev: ATA device
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* @mask: mode mask
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*
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* The Marvell bridge chips used on the HighPoint SATA cards do not seem
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* to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
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*/
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static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask)
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{
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if (ata_id_is_sata(adev->id))
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mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
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return mask;
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}
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/**
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* hpt3x2n_cable_detect - Detect the cable type
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* @ap: ATA port to detect on
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*
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* Return the cable type attached to this port
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*/
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static int hpt3x2n_cable_detect(struct ata_port *ap)
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{
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u8 scr2, ata66;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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pci_read_config_byte(pdev, 0x5B, &scr2);
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pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
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udelay(10); /* debounce */
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/* Cable register now active */
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pci_read_config_byte(pdev, 0x5A, &ata66);
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/* Restore state */
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pci_write_config_byte(pdev, 0x5B, scr2);
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if (ata66 & (2 >> ap->port_no))
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return ATA_CBL_PATA40;
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else
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return ATA_CBL_PATA80;
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}
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/**
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* hpt3x2n_pre_reset - reset the hpt3x2n bus
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* @link: ATA link to reset
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* @deadline: deadline jiffies for the operation
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*
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* Perform the initial reset handling for the 3x2n series controllers.
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* Reset the hardware and state machine,
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*/
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static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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/* Reset the state machine */
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pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
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udelay(100);
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return ata_sff_prereset(link, deadline);
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}
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static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev,
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u8 mode)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u32 addr1, addr2;
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u32 reg, timing, mask;
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u8 fast;
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addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
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addr2 = 0x51 + 4 * ap->port_no;
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/* Fast interrupt prediction disable, hold off interrupt disable */
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pci_read_config_byte(pdev, addr2, &fast);
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fast &= ~0x07;
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pci_write_config_byte(pdev, addr2, fast);
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/* Determine timing mask and find matching mode entry */
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if (mode < XFER_MW_DMA_0)
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mask = 0xcfc3ffff;
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else if (mode < XFER_UDMA_0)
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mask = 0x31c001ff;
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else
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mask = 0x303c0000;
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timing = hpt3x2n_find_mode(ap, mode);
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pci_read_config_dword(pdev, addr1, ®);
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reg = (reg & ~mask) | (timing & mask);
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pci_write_config_dword(pdev, addr1, reg);
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}
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/**
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* hpt3x2n_set_piomode - PIO setup
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* @ap: ATA interface
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* @adev: device on the interface
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*
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* Perform PIO mode setup.
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*/
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static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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hpt3x2n_set_mode(ap, adev, adev->pio_mode);
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}
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/**
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* hpt3x2n_set_dmamode - DMA timing setup
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* @ap: ATA interface
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* @adev: Device being configured
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*
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* Set up the channel for MWDMA or UDMA modes.
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*/
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static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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hpt3x2n_set_mode(ap, adev, adev->dma_mode);
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}
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/**
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* hpt3x2n_bmdma_end - DMA engine stop
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* @qc: ATA command
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*
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* Clean up after the HPT3x2n and later DMA engine
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*/
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static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int mscreg = 0x50 + 2 * ap->port_no;
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u8 bwsr_stat, msc_stat;
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pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
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pci_read_config_byte(pdev, mscreg, &msc_stat);
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if (bwsr_stat & (1 << ap->port_no))
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pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
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ata_bmdma_stop(qc);
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}
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/**
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* hpt3x2n_set_clock - clock control
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* @ap: ATA port
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* @source: 0x21 or 0x23 for PLL or PCI sourced clock
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*
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* Switch the ATA bus clock between the PLL and PCI clock sources
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* while correctly isolating the bus and resetting internal logic
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*
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* We must use the DPLL for
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* - writing
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* - second channel UDMA7 (SATA ports) or higher
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* - 66MHz PCI
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*
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* or we will underclock the device and get reduced performance.
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*/
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static void hpt3x2n_set_clock(struct ata_port *ap, int source)
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{
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void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8;
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/* Tristate the bus */
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iowrite8(0x80, bmdma+0x73);
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iowrite8(0x80, bmdma+0x77);
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/* Switch clock and reset channels */
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iowrite8(source, bmdma+0x7B);
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iowrite8(0xC0, bmdma+0x79);
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/* Reset state machines, avoid enabling the disabled channels */
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iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70);
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iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74);
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/* Complete reset */
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iowrite8(0x00, bmdma+0x79);
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/* Reconnect channels to bus */
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iowrite8(0x00, bmdma+0x73);
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iowrite8(0x00, bmdma+0x77);
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}
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static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
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{
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long flags = (long)ap->host->private_data;
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/* See if we should use the DPLL */
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if (writing)
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return USE_DPLL; /* Needed for write */
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if (flags & PCI66)
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return USE_DPLL; /* Needed at 66Mhz */
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return 0;
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}
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static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_port *alt = ap->host->ports[ap->port_no ^ 1];
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int rc, flags = (long)ap->host->private_data;
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int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
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/* First apply the usual rules */
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rc = ata_std_qc_defer(qc);
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if (rc != 0)
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return rc;
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if ((flags & USE_DPLL) != dpll && alt->qc_active)
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return ATA_DEFER_PORT;
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return 0;
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}
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static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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int flags = (long)ap->host->private_data;
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int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
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if ((flags & USE_DPLL) != dpll) {
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flags &= ~USE_DPLL;
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flags |= dpll;
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ap->host->private_data = (void *)(long)flags;
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hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
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}
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return ata_bmdma_qc_issue(qc);
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}
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static struct scsi_host_template hpt3x2n_sht = {
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ATA_BMDMA_SHT(DRV_NAME),
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};
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/*
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* Configuration for HPT302N/371N.
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*/
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static struct ata_port_operations hpt3xxn_port_ops = {
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.inherits = &ata_bmdma_port_ops,
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.bmdma_stop = hpt3x2n_bmdma_stop,
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.qc_defer = hpt3x2n_qc_defer,
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.qc_issue = hpt3x2n_qc_issue,
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.cable_detect = hpt3x2n_cable_detect,
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.set_piomode = hpt3x2n_set_piomode,
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.set_dmamode = hpt3x2n_set_dmamode,
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.prereset = hpt3x2n_pre_reset,
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};
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/*
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* Configuration for HPT372N. Same as 302N/371N but we have a mode filter.
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*/
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static struct ata_port_operations hpt372n_port_ops = {
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.inherits = &hpt3xxn_port_ops,
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.mode_filter = &hpt372n_filter,
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};
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/**
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* hpt3xn_calibrate_dpll - Calibrate the DPLL loop
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* @dev: PCI device
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*
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* Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
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* succeeds
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*/
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static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
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{
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u8 reg5b;
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u32 reg5c;
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int tries;
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for (tries = 0; tries < 0x5000; tries++) {
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udelay(50);
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pci_read_config_byte(dev, 0x5b, ®5b);
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if (reg5b & 0x80) {
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/* See if it stays set */
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for (tries = 0; tries < 0x1000; tries++) {
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pci_read_config_byte(dev, 0x5b, ®5b);
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/* Failed ? */
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if ((reg5b & 0x80) == 0)
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return 0;
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}
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/* Turn off tuning, we have the DPLL set */
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pci_read_config_dword(dev, 0x5c, ®5c);
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pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
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return 1;
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}
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}
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/* Never went stable */
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return 0;
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}
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static int hpt3x2n_pci_clock(struct pci_dev *pdev)
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{
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unsigned long freq;
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u32 fcnt;
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unsigned long iobase = pci_resource_start(pdev, 4);
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fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */
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if ((fcnt >> 12) != 0xABCDE) {
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int i;
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u16 sr;
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u32 total = 0;
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pr_warning(DRV_NAME ": BIOS clock data not set.\n");
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/* This is the process the HPT371 BIOS is reported to use */
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for (i = 0; i < 128; i++) {
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pci_read_config_word(pdev, 0x78, &sr);
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total += sr & 0x1FF;
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udelay(15);
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}
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fcnt = total / 128;
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}
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fcnt &= 0x1FF;
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freq = (fcnt * 77) / 192;
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/* Clamp to bands */
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if (freq < 40)
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return 33;
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if (freq < 45)
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return 40;
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if (freq < 55)
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return 50;
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return 66;
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}
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/**
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* hpt3x2n_init_one - Initialise an HPT37X/302
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* @dev: PCI device
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* @id: Entry in match table
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*
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* Initialise an HPT3x2n device. There are some interesting complications
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* here. Firstly the chip may report 366 and be one of several variants.
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* Secondly all the timings depend on the clock for the chip which we must
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* detect and look up
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*
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* This is the known chip mappings. It may be missing a couple of later
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* releases.
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*
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* Chip version PCI Rev Notes
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* HPT372 4 (HPT366) 5 Other driver
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* HPT372N 4 (HPT366) 6 UDMA133
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* HPT372 5 (HPT372) 1 Other driver
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* HPT372N 5 (HPT372) 2 UDMA133
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* HPT302 6 (HPT302) * Other driver
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* HPT302N 6 (HPT302) > 1 UDMA133
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* HPT371 7 (HPT371) * Other driver
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* HPT371N 7 (HPT371) > 1 UDMA133
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* HPT374 8 (HPT374) * Other driver
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* HPT372N 9 (HPT372N) * UDMA133
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*
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* (1) UDMA133 support depends on the bus clock
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*/
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static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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/* HPT372N - UDMA133 */
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static const struct ata_port_info info_hpt372n = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA6,
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.port_ops = &hpt372n_port_ops
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};
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/* HPT302N and HPT371N - UDMA133 */
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static const struct ata_port_info info_hpt3xxn = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA6,
|
|
.port_ops = &hpt3xxn_port_ops
|
|
};
|
|
const struct ata_port_info *ppi[] = { &info_hpt3xxn, NULL };
|
|
u8 rev = dev->revision;
|
|
u8 irqmask;
|
|
unsigned int pci_mhz;
|
|
unsigned int f_low, f_high;
|
|
int adjust;
|
|
unsigned long iobase = pci_resource_start(dev, 4);
|
|
void *hpriv = (void *)USE_DPLL;
|
|
int rc;
|
|
|
|
rc = pcim_enable_device(dev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
switch (dev->device) {
|
|
case PCI_DEVICE_ID_TTI_HPT366:
|
|
/* 372N if rev >= 6 */
|
|
if (rev < 6)
|
|
return -ENODEV;
|
|
goto hpt372n;
|
|
case PCI_DEVICE_ID_TTI_HPT371:
|
|
/* 371N if rev >= 2 */
|
|
if (rev < 2)
|
|
return -ENODEV;
|
|
break;
|
|
case PCI_DEVICE_ID_TTI_HPT372:
|
|
/* 372N if rev >= 2 */
|
|
if (rev < 2)
|
|
return -ENODEV;
|
|
goto hpt372n;
|
|
case PCI_DEVICE_ID_TTI_HPT302:
|
|
/* 302N if rev >= 2 */
|
|
if (rev < 2)
|
|
return -ENODEV;
|
|
break;
|
|
case PCI_DEVICE_ID_TTI_HPT372N:
|
|
hpt372n:
|
|
ppi[0] = &info_hpt372n;
|
|
break;
|
|
default:
|
|
pr_err(DRV_NAME ": PCI table is bogus, please report (%d).\n",
|
|
dev->device);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Ok so this is a chip we support */
|
|
|
|
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
|
|
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
|
|
pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
|
|
pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
|
|
|
|
pci_read_config_byte(dev, 0x5A, &irqmask);
|
|
irqmask &= ~0x10;
|
|
pci_write_config_byte(dev, 0x5a, irqmask);
|
|
|
|
/*
|
|
* HPT371 chips physically have only one channel, the secondary one,
|
|
* but the primary channel registers do exist! Go figure...
|
|
* So, we manually disable the non-existing channel here
|
|
* (if the BIOS hasn't done this already).
|
|
*/
|
|
if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
|
|
u8 mcr1;
|
|
pci_read_config_byte(dev, 0x50, &mcr1);
|
|
mcr1 &= ~0x04;
|
|
pci_write_config_byte(dev, 0x50, mcr1);
|
|
}
|
|
|
|
/*
|
|
* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
|
|
* 50 for UDMA100. Right now we always use 66
|
|
*/
|
|
|
|
pci_mhz = hpt3x2n_pci_clock(dev);
|
|
|
|
f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
|
|
f_high = f_low + 2; /* Tolerance */
|
|
|
|
pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
|
|
/* PLL clock */
|
|
pci_write_config_byte(dev, 0x5B, 0x21);
|
|
|
|
/* Unlike the 37x we don't try jiggling the frequency */
|
|
for (adjust = 0; adjust < 8; adjust++) {
|
|
if (hpt3xn_calibrate_dpll(dev))
|
|
break;
|
|
pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
|
|
}
|
|
if (adjust == 8) {
|
|
pr_err(DRV_NAME ": DPLL did not stabilize!\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
pr_info(DRV_NAME ": bus clock %dMHz, using 66MHz DPLL.\n", pci_mhz);
|
|
|
|
/*
|
|
* Set our private data up. We only need a few flags
|
|
* so we use it directly.
|
|
*/
|
|
if (pci_mhz > 60)
|
|
hpriv = (void *)(PCI66 | USE_DPLL);
|
|
|
|
/*
|
|
* On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
|
|
* the MISC. register to stretch the UltraDMA Tss timing.
|
|
* NOTE: This register is only writeable via I/O space.
|
|
*/
|
|
if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
|
|
outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
|
|
|
|
/* Now kick off ATA set up */
|
|
return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0);
|
|
}
|
|
|
|
static const struct pci_device_id hpt3x2n[] = {
|
|
{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
|
|
{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
|
|
{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
|
|
{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
|
|
{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
|
|
|
|
{ },
|
|
};
|
|
|
|
static struct pci_driver hpt3x2n_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = hpt3x2n,
|
|
.probe = hpt3x2n_init_one,
|
|
.remove = ata_pci_remove_one
|
|
};
|
|
|
|
static int __init hpt3x2n_init(void)
|
|
{
|
|
return pci_register_driver(&hpt3x2n_pci_driver);
|
|
}
|
|
|
|
static void __exit hpt3x2n_exit(void)
|
|
{
|
|
pci_unregister_driver(&hpt3x2n_pci_driver);
|
|
}
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3xxN");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DEVICE_TABLE(pci, hpt3x2n);
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
module_init(hpt3x2n_init);
|
|
module_exit(hpt3x2n_exit);
|