96 lines
2.6 KiB
C
96 lines
2.6 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_bios.h"
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#include "nouveau_pm.h"
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/*XXX: boards using limits 0x40 need fixing, the register layout
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* is correct here, but, there's some other funny magic
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* that modifies things, so it's not likely we'll set/read
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* the correct timings yet.. working on it...
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*/
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struct nva3_pm_state {
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struct pll_lims pll;
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int N, M, P;
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};
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int
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nva3_pm_clock_get(struct drm_device *dev, u32 id)
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{
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struct pll_lims pll;
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int P, N, M, ret;
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u32 reg;
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ret = get_pll_limits(dev, id, &pll);
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if (ret)
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return ret;
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reg = nv_rd32(dev, pll.reg + 4);
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P = (reg & 0x003f0000) >> 16;
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N = (reg & 0x0000ff00) >> 8;
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M = (reg & 0x000000ff);
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return pll.refclk * N / M / P;
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}
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void *
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nva3_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,
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u32 id, int khz)
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{
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struct nva3_pm_state *state;
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int dummy, ret;
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state = kzalloc(sizeof(*state), GFP_KERNEL);
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if (!state)
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return ERR_PTR(-ENOMEM);
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ret = get_pll_limits(dev, id, &state->pll);
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if (ret < 0) {
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kfree(state);
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return (ret == -ENOENT) ? NULL : ERR_PTR(ret);
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}
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ret = nv50_calc_pll2(dev, &state->pll, khz, &state->N, &dummy,
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&state->M, &state->P);
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if (ret < 0) {
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kfree(state);
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return ERR_PTR(ret);
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}
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return state;
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}
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void
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nva3_pm_clock_set(struct drm_device *dev, void *pre_state)
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{
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struct nva3_pm_state *state = pre_state;
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u32 reg = state->pll.reg;
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nv_wr32(dev, reg + 4, (state->P << 16) | (state->N << 8) | state->M);
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kfree(state);
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}
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